参数资料
型号: MCF51QF128VHS
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: FLASH, 50 MHz, MICROCONTROLLER, QCC44
封装: 5 X 5 MM, QFN-44
文件页数: 9/72页
文件大小: 1031K
代理商: MCF51QF128VHS
5.3 Switching electrical specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
50
MHz
fSYS_USB
System and core clock when USB in operation
20
MHz
fBUS
Bus clock
25
MHz
FB_CLK
Mini-FlexBus clock
25
MHz
fLPTMR
LPTMR clock
25
MHz
VLPR mode
fSYS
System and core clock
2
MHz
fBUS
Bus clock
1
MHz
FB_CLK
Mini-FlexBus clock
1
MHz
fLPTMR
LPTMR clock1
25
MHz
1. A maximum frequency of 25 MHz for the LPTMR in VLPR mode is possible when the LPTMR is configured for pulse
counting mode and is driven externally via the LPTMR_ALT1, LPTMR_ALT2, or LPTMR_ALT3 pin.
5.3.1 General Switching Specifications
These general purpose specifications apply to all signals configured for EGPIO, MTIM,
CMT, PDB, IRQ, and I2C signals. The conditions are 50 pf load, VDD = 1.71 V to 3.6 V,
and full temperature range. The GPIO are set for high drive, no slew rate control, and no
input filter, digital or analog, unless otherwise specified.
Table 10. EGPIO General Control Timing
Symbol
Description
Min.
Max.
Unit
G1
Bus clock from CLK_OUT pin high to GPIO output valid
32
ns
G2
Bus clock from CLK_OUT pin high to GPIO output invalid
(output hold)
1
ns
G3
GPIO input valid to bus clock high
28
ns
G4
Bus clock from CLK_OUT pin high to GPIO input invalid
4
ns
GPIO pin interrupt pulse width (digital glitch filter disabled)
Synchronous path1
1.5
Bus
clock
cycles
Table continues on the next page...
Nonswitching electrical specifications
MCF51JF128 Advance Information Data Sheet, Rev. 3, 08/2011.
Freescale Semiconductor, Inc.
Preliminary
17
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