参数资料
型号: MCF5211CEP66
厂商: Freescale Semiconductor
文件页数: 54/56页
文件大小: 0K
描述: IC MCU 128K FLASH 66MHZ 64-QFN
标准包装: 260
系列: MCF521x
核心处理器: Coldfire V2
芯体尺寸: 32-位
速度: 66MHz
连通性: CAN,I²C,SPI,UART/USART
外围设备: DMA,LVD,POR,PWM,WDT
输入/输出数: 33
程序存储器容量: 128KB(128K x 8)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 8x12b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 64-VFQFN 裸露焊盘
包装: 托盘
配用: M5211DEMO-ND - KIT DEMO FOR MCF5211
MCF5213 Family Configurations
MCF5213 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
7
— Programmable center or left aligned outputs on individual channels
— Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
— Emergency shutdown
Two periodic interrupt timers (PITs)
— 16-bit counter
— Selectable as free running or count down
Software watchdog timer
— 32-bit counter
— Low-power mode support
Clock generation features
— One to 48 MHz crystal, 8 MHz on-chip relaxation oscillator, or external oscillator reference options
— Trimmed relaxation oscillator
— Two to 10 MHz reference frequency for normal PLL mode with a pre-divider programmable from 1 to 8
— System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator
— Low power modes supported
—2n (n
≤ 0 ≤ 15) low-power divider for extremely low frequency operation
Interrupt controller
— Uniquely programmable vectors for all interrupt sources
— Fully programmable level and priority for all peripheral interrupt sources
— Seven external interrupt signals with fixed level and priority
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low-power modes
DMA controller
— Four fully programmable channels
— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4
×32-bit)
burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)
Reset
— Separate reset in and reset out signals
— Seven sources of reset:
Power-on reset (POR)
External
–Software
Watchdog
Loss of clock
Loss of lock
Low-voltage detection (LVD)
— Status flag indication of source of last reset
Chip integration module (CIM)
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