参数资料
型号: MCF5213CAF66
厂商: Freescale Semiconductor
文件页数: 13/56页
文件大小: 0K
描述: IC MCU 256K FLASH 66MHZ 100-LQFP
标准包装: 90
系列: MCF521x
核心处理器: Coldfire V2
芯体尺寸: 32-位
速度: 66MHz
连通性: CAN,I²C,SPI,UART/USART
外围设备: DMA,LVD,POR,PWM,WDT
输入/输出数: 55
程序存储器容量: 256KB(256K x 8)
程序存储器类型: 闪存
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 8x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
包装: 托盘
配用: M5213EVBE-ND - KIT EVAL FOR MCF5213
M5211DEMO-ND - KIT DEMO FOR MCF5211
MCF5213 ColdFire Microcontroller, Rev. 3
MCF5213 Family Configurations
Freescale Semiconductor
20
1.2
Reset Signals
Table 4 describes signals used to reset the chip or as a reset indication.
1.3
PLL and Clock Signals
Table 5 describes signals used to support the on-chip clock generation circuitry.
1.4
Mode Selection
Table 6 describes signals used in mode selection; Table 7 describes the particular clocking modes.
Table 4. Reset Signals
Signal Name
Abbreviation
Function
I/O
Reset In
RSTI
Primary reset input to the device. Asserting RSTI for at least 8 CPU
clock cycles immediately resets the CPU and peripherals.
I
Reset Out
RSTO
Driven low for 1024 CPU clocks after the reset source has deasserted.
O
Table 5. PLL and Clock Signals
Signal Name
Abbreviation
Function
I/O
External Clock In
EXTAL
Crystal oscillator or external clock input except when the on-chip
relaxation oscillator is used.
I
Crystal
XTAL
Crystal oscillator output except when CLKMOD1=1, then sampled as
part of the clock mode selection mechanism.
O
Clock Out
CLKOUT
This output signal reflects the internal system clock.
O
Table 6. Mode Selection Signals
Signal Name
Abbreviation
Function
I/O
Clock Mode Selection
CLKMOD[1:0]
Selects the clock boot mode.
I
Reset Configuration
RCON
The Serial Flash Programming mode is entered by asserting the
RCON pin (with the TEST pin negated) as the chip comes out of
reset. During this mode, the EzPort has access to the flash memory
which can be programmed from an external device.
Test
TEST
Reserved for factory testing only and in normal modes of operation
should be connected to VSS to prevent unintentional activation of
test functions.
I
Table 7. Clocking Modes
CLKMOD[1:0]
XTAL
Configure the clock mode.
00
0
PLL disabled, clock driven by external oscillator
00
1
PLL disabled, clock driven by on-chip oscillator
01
N/A
PLL disabled, clock driven by crystal
10
0
PLL in normal mode, clock driven by external oscillator
10
1
PLL in normal mode, clock driven by on-chip oscillator
11
N/A
PLL in normal mode, clock driven by crystal
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