参数资料
型号: MCF5213CAF66
厂商: Freescale Semiconductor
文件页数: 16/56页
文件大小: 0K
描述: IC MCU 256K FLASH 66MHZ 100-LQFP
标准包装: 90
系列: MCF521x
核心处理器: Coldfire V2
芯体尺寸: 32-位
速度: 66MHz
连通性: CAN,I²C,SPI,UART/USART
外围设备: DMA,LVD,POR,PWM,WDT
输入/输出数: 55
程序存储器容量: 256KB(256K x 8)
程序存储器类型: 闪存
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 8x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
包装: 托盘
配用: M5213EVBE-ND - KIT EVAL FOR MCF5213
M5211DEMO-ND - KIT DEMO FOR MCF5211
MCF5213 Family Configurations
MCF5213 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
23
1.11
General Purpose Timer Signals
Table 14 describes the general purpose timer signals.
1.12
Pulse Width Modulator Signals
Table 15 describes the PWM signals.
1.13
Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and the BDM logic.
Table 14. GPT Signals
Signal Name
Abbreviation
Function
I/O
General Purpose Timer
Input/Output
GPT[3:0]
Inputs to or outputs from the general purpose timer module.
I/O
Table 15. PWM Signals
Signal Name
Abbreviation
Function
I/O
PWM Output Channels
PWM[7:0]
Pulse width modulated output for PWM channels.
O
Table 16. Debug Support Signals
Signal Name
Abbreviation
Function
I/O
JTAG Enable
JTAG_EN
Select between debug module and JTAG signals at reset.
I
Test Reset
TRST
This active-low signal is used to initialize the JTAG logic
asynchronously.
I
Test Clock
TCLK
Used to synchronize the JTAG logic.
I
Test Mode Select
TMS
Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
I
Test Data Input
TDI
Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
I
Test Data Output
TDO
Serial output for test instructions and data. TDO is tri-stateable and is
actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
O
Development Serial
Clock
DSCLK
Development Serial Clock - Internally synchronized input. (The logic
level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication
port to the debug module during packet transfers. Maximum frequency
is PSTCLK/5. At the synchronized rising edge of DSCLK, the data
input on DSI is sampled and DSO changes state.
I
Breakpoint
BKPT
Breakpoint - Input used to request a manual breakpoint. Assertion of
BKPT puts the processor into a halted state after the current
instruction completes. Halt status is reflected on processor
status/debug data signals (PST[3:0] and PSTDDATA[7:0]) as the
value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality),
asserting BKPT generates a debug interrupt exception in the
processor.
I
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