参数资料
型号: MCF5233CVM100
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 100 MHz, RISC PROCESSOR, PBGA256
封装: MAPBGA-256
文件页数: 18/76页
文件大小: 2665K
代理商: MCF5233CVM100
MOTOROLA
MCF523x Integrated Microprocessor Hardware Specifications
25
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Primary Functions
2.2.11 Queued Serial Peripheral Interface (QSPI)
Table 12 describes QSPI signals.
2.2.12 UART Module Signals
The UART modules use the signals in this section for data. The baud rate clock inputs are not supported.
Table 12. Queued Serial Peripheral Interface (QSPI) Signals
Signal Name
Abbreviation
Function
I/O
QSPI Syncrhonous
Serial Output
QSPI_DOUT
Provides the serial data from the QSPI and can be programmed to be
driven on the rising or falling edge of QSPI_CLK. Each byte is sent
msb first.
This pin can also be configured as GPIO.
O
QSPI Synchronous
Serial Data Input
QSPI_DIN
Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK. Each byte is
written to RAM lsb first.
This pin can also be configured as GPIO or as I2C data signal
I2C_SDA.
I
QSPI Serial Clock
QSPI_CLK
Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable. The output frequency is programmed
according to the following formula, in which n can be any value
between 1 and 255:
SPI_CLK = fsys/2 ÷ n
This pin can also be configured as GPIO or as I2C clock signal
I2C_SCL.
O
Synchronous
Peripheral Chip Selects
QSPI_CS[1:0] Provide QSPI peripheral chip selects that can be programmed to be
active high or low. QSPI_CS1 can also be configured as SDRAM
clock enable signal SD_CKE.
These pins can also be configured as GPIO.
O
Table 13. UART Module Signals
Signal Name
Abbreviation
Function
I/O
Transmit Serial Data
Output
U2TXD/U1TXD
/U0TXD
Transmitter serial data outputs for the UART modules. The output is
held high (mark condition) when the transmitter is disabled, idle, or in
the local loopback mode. Data is shifted out, lsb first, on this pin at the
falling edge of the serial clock source.
U1TXD can also be configured as Controller Area Network Transmit
data output CAN0TX.
U2TXD can also be configured as Controller Area Network Transmit
data output CAN1TX.
All pins can also be configured as GPIO.
O
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