参数资料
型号: MCF5233CVM100
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 100 MHz, RISC PROCESSOR, PBGA256
封装: MAPBGA-256
文件页数: 62/76页
文件大小: 2665K
代理商: MCF5233CVM100
MOTOROLA
MCF523x Integrated Microprocessor Hardware Specifications
65
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Fast Ethernet AC Timing Specifications
Figure 18 shows timing for the values in Table 51 and Table 52.
Figure 18. I2C Input/Output Timings
6.10 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
6.10.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER,
and ERXCLK)
The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
ERXCLK frequency.
Table 53 lists MII receive channel timings.
I7 1
Data setup time
2
tcyc
I8 1
Start condition setup time (for repeated start
condition only)
20
tcyc
I9 1
Stop condition setup time
10
tcyc
1
Note: Output numbers depend on the value programmed into the IFDR; an IFDR
programmed with the maximum frequency (IFDR = 0x20) results in minimum output
timings as shown in Table 52. The I2C interface is designed to scale the actual data
transition time to move it to the middle of the I2C_SCL low period. The actual position is
affected by the prescale and division values programmed into the IFDR; however, the
numbers given in Table 52 are minimum values.
2
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can
only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends
on external signal capacitance and pull-up resistor values.
3
Specified at a nominal 50-pF load.
Table 52. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I2
I6
I1
I4
I7
I8
I9
I5
I3
I2C_SCL
I2C_SDA
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