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| 型号： | MCF5270CAB100 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP160 |
| 封装： | ROHS COMPLIANT, PLASTIC, QFP-160 |
| 文件页数： | 10/42页 |
| 文件大小： | 554K |
| 代理商： | MCF5270CAB100 |
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MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor
18
7.2
Thermal Characteristics
The below table lists thermal resistance values.
2
This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid application of
any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.,
either VSS or OVDD).
3
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages,
then use the larger of the two values.
4
All functional non-supply pins are internally clamped to VSS and OVDD.
5
Power supply must maintain regulation within operating OVDD range during instantaneous
and operating maximum current conditions. If positive injection current (Vin > OVDD) is greater
than IDD, the injection current may flow out of OVDD and could result in external power supply
going out of regulation. Insure external OVDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the processor is not consuming power
(ex; no clock).Power supply must maintain regulation within operating OVDD range during
instantaneous and operating maximum current conditions.
Table 8. Thermal Characteristics
Characteristic
Symbol
196
MAPBGA
160QFP
Unit
Junction to ambient, natural convection
Four layer board (2s2p)
θ
JMA
321,2
1
θ
JMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.
Motorola recommends the use of
θ
JmA and power dissipation specifications in the system design to prevent
device junction temperatures from exceeding the rated specification. System designers should be aware that
device junction temperatures can be significantly influenced by board layout and surrounding devices.
Conformance to the device junction temperature specification can be verified by physical measurement in the
customer’s system using the
Ψ
jt parameter, the device power dissipation, and the method described in
EIA/JESD Standard 51-2.
2
Per JEDEC JESD51-6 with the board horizontal.
401,2
°C/W
Junction to ambient (@200 ft/min)
Four layer board (2s2p)
θ
JMA
291,2
361,2
°C/W
Junction to board
θ
JB
203
3
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8.
Board temperature is measured on the top surface of the board near the package.
253
°C/W
Junction to case
θ
JC
104
4
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
104
°C/W
Junction to top of package
Ψ
jt
21,5
5
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written in conformance with Psi-JT.
21,5
°C/W
Maximum operating junction temperature
Tj
104
105
oC
The average chip-junction temperature (TJ) in °C can be obtained from:
(1)
Where:
T
J
T
A
P
D
Θ
JMA
×
()
+
=
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