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参数资料
| 型号： | MCF5270CAB100 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP160 |
| 封装： | ROHS COMPLIANT, PLASTIC, QFP-160 |
| 文件页数： | 13/42页 |
| 文件大小： | 554K |
| 代理商： | MCF5270CAB100 |
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MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor
20
7.4
Oscillator and PLLMRFM Electrical Characteristics
Load Capacitance4
Low drive strength
High drive strength
CL
—
25
50
pF
Core Operating Supply Current 5
Master Mode
IDD
—
135
150
mA
Pad Operating Supply Current
Master Mode
Low Power Modes
OIDD
—
100
TBD
—
mA
μA
DC Injection Current 3, 6, 7, 8
VNEGCLAMP =VSS– 0.3 V, VPOSCLAMP = VDD + 0.3
Single Pin Limit
Total processor Limit, Includes sum of all stressed pins
IIC
–1.0
–10
1.0
10
mA
1
Refer to Table 10 for additional PLL specifications.
2
Refer to the MCF5271 signals section for pins having weak internal pull-up devices.
3
This parameter is characterized before qualification rather than 100% tested.
4
pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces require
transmission line analysis to determine proper drive strength and termination. See High Speed Signal Propagation:
Advanced Black Magic by Howard W. Johnson for design guidelines.
5
Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load.
6
All functional non-supply pins are internally clamped to VSS and their respective VDD.
7
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
8
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Insure external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the processor is not consuming power. Examples are: if no system
clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, system clock
is not present during the power-up sequence until the PLL has attained lock.
Table 10. HiP7 PLLMRFM Electrical Specifications1
Num
Characteristic
Symbol
Min.
Value
Max.
Value
Unit
1
PLL Reference Frequency Range
Crystal reference
External reference
1:1 mode (NOTE: fsys/2 = 2 × fref_1:1)
fref_crystal
fref_ext
fref_1:1
8
24
25
75
MHz
2
Core frequency
CLKOUT Frequency 2
External reference
On-Chip PLL Frequency
fsys
fsys/2
0
fref ÷ 32
150
75
MHz
3
Loss of Reference Frequency 3, 5
fLOR
100
1000
kHz
4
Self Clocked Mode Frequency 4, 5
fSCM
10.25
15.25
MHz
5
Crystal Start-up Time 5, 6
tcst
—10
ms
Table 9. DC Electrical Specifications1 (continued)
Characteristic
Symbol
Min
Typical
Max
Unit
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