
General Operation
MCF5282 Coldfire Microcontroller Reference Manual, Rev. 2.2
Freescale Semiconductor
3-3
3.3
General Operation
The MAC speeds execution of ColdFire integer multiply instructions (MULS and MULU) and provides
additional functionality for multiply-accumulate operations. By executing MULS and MULU in the MAC,
execution times are minimized and deterministic compared to the 2-bit/cycle algorithm with early
termination that the OEP normally uses if no MAC hardware is present.
The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed
by the addition or subtraction of the product to or from the value in accumulator. Optionally, the product
may be shifted left or right by 1 bit before addition or subtraction. Hardware support for saturation
arithmetic can be enabled to minimize software overhead when dealing with potential overflow conditions.
Multiply-accumulate operations support 16- or 32-bit input operands of the following formats:
Signed integers
Unsigned integers
Signed, fixed-point, fractional numbers
All arithmetic operations use register-based input operands, and summed values are stored internally in
accumulator. Thus, an additional move instruction is needed to store data in a general-purpose register.
One new feature found in EMAC instructions is the ability to choose the upper or lower word of a register
as a 16-bit input operand. This is useful in filtering operations if one data register is loaded with the input
data and another is loaded with the coefficient. Two 16-bit multiply accumulates can be performed without
fetching additional operands between instructions by alternating the word choice during the calculations.
The need to move large amounts of data presents an obstacle to obtaining high throughput rates in DSP
engines. New and existing ColdFire instructions can accommodate these requirements. A MOVEM
instruction can move large blocks of data efficiently by generating line-sized burst references. The ability
to simultaneously load an operand from memory into a register and execute a MAC instruction makes
some DSP operations such as filtering and convolution more manageable.
The programming model includes a 16-bit mask register (MASK), which can optionally be used to
generate an operand address during MAC + MOVE instructions. The application of this register with
auto-increment addressing mode supports efficient implementation of circular data queues for memory
operands.
The additional MAC status register (MACSR) contains a 4-bit operational mode field and condition flags.
Operational mode bits control whether operands are signed or unsigned and whether they are treated as
integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding
is performed. Negative, zero, and overflow condition flags are also provided.
3.4
Memory Map/Register Set
Figure 3-4. MAC Register Set
3.4.1
MAC Status Register (MACSR)
MACSR functionality is organized as follows:
MACSR[7–4] defines the operating configuration of the MAC unit.
31
0
MACSR
MAC status register
ACC
MAC accumulator
MASK
MAC mask register