
MCF5282 Coldfire Microcontroller Reference Manual, Rev. 2.2
Freescale Semiconductor
4-1
Chapter 4
Cache
This chapter describes the MCF5282 cache operation.
4.1
Cache Features
Configurable as instruction, data, or split instruction/data cache
2-Kbyte direct-mapped cache
Single-cycle access on cache hits
Physically located on the Coldfire core's high-speed local bus
Nonblocking design to maximize performance
Separate instruction and data 16-Byte line-fill buffers
Configurable instruction cache miss-fetch algorithm
4.2
Cache Physical Organization
The cache is a direct-mapped single-cycle memory. It may be configured as an instruction cache, a
write-through data cache, or a split instruction/data cache. The cache storage is organized as 128 lines,
each containing 16 bytes. The memory storage consists of a 128-entry tag array (containing addresses and
a valid bit), and a data array containing 2 Kbytes, organized as 512 x 32 bits.
Cache configuration is controlled by bits in the cache control register (CACR) that is detailed later in this
chapter. For the instruction or data-only configurations, only the associated instruction or data line-fill
buffer is used. For the split cache configuration, one-half of the tag and storage arrays is used for an
instruction cache and one-half is used for a data cache. The split cache configuration uses both the
instruction and the data line-fill buffers. The core’s local bus is a unified bus used for both instruction and
data fetches. Therefore, the cache can have only one fetch, either instruction or data, active at one time.
For the instruction- or data-only configurations, the cache tag and storage arrays are accessed in parallel:
fetch address bits [10:4] addressing the tag array and fetch address bits [10:2] addressing the storage array.
For the split cache configuration, the cache tag and storage arrays are accessed in parallel. The msb of the
tag array address is set for instruction fetches and cleared for operand fetches; fetch address bits [9:4]
provide the rest of the tag array address. The tag array outputs the address mapped to the given cache
location along with the valid bit for the line. This address field is compared to bits [31:11] for instruction-
or data-only configurations and to bits [31:10] for a split configuration of the fetch address from the local
bus to determine if a cache hit has occurred. If the desired address is mapped into the cache memory, the
output of the storage array is driven onto the ColdFire core's local data bus, thereby completing the access
in a single cycle.
The tag array maintains a single valid bit per line entry. Accordingly, only entire 16-byte lines are loaded
into the cache.
The cache also contains separate 16-byte instruction and data line-fill buffers that provide temporary
storage for the last line fetched in response to a cache miss. With each fetch, the contents of the associated
line fill buffer are examined. Thus, each fetch address examines both the tag memory array and the
associated line fill buffer to see if the desired address is mapped into either hardware resource. A cache hit
in either the memory array or the associated line-fill buffer is serviced in a single cycle. Because the line
fill buffer maintains valid bits on a longword basis, hits in the buffer can be serviced immediately without
waiting for the entire line to be fetched.