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参数资料
| 型号： | MCF5481CZP166 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388 |
| 封装： | 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388 |
| 文件页数： | 26/96页 |
| 文件大小： | 2006K |
| 代理商： | MCF5481CZP166 |
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32
MCF548x Integrated Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Description
1.5.1.3
PCI Controller Signals
1.5.1.3.1
PCI Address/Data Bus (PCIAD[31:0])
The PCIAD[31:0] lines are a time-multiplexed address data bus. The address is presented on the bus during
the address phase while the data is presented on the bus during one or more data phases.
If the FlexBus is used in 32-bit address/32-bit data non-multiplexed mode, PCIAD[31:0] are used as a 32-bit
address for FlexBus transfers.
1.5.1.3.2
Command/Byte Enables (PCICXBE[3:0])
The PCICXBE[3:0] lines are time multiplexed. The PCI command is presented during the address phase
and the byte enables are presented during the data phase.
1.5.1.3.3
Device Select (PCIDEVSEL)
The PCIDEVSEL signal is asserted active low when the MCF548x decodes that it is the target of a PCI
transaction from the address presented on the PCI bus during the address phase.
1.5.1.3.4
Frame (PCIFRM)
The PCIFRM signal is asserted by a PCI initiator to indicate the beginning of a transaction. It is negated
when the initiator is ready to complete the final data phase.
1.5.1.3.5
Initialization Device Select (PCIIDSEL)
The PCIIDSEL signal is asserted during a PCI type-0 configuration cycle to address the PCI configuration
header.
1.5.1.3.6
Initiator Ready (PCIIRDY)
The PCIIRDY signal is asserted to indicate that the PCI initiator is ready to transfer data. During a write
operation, assertion indicates that the master is driving valid data on the bus. During a read operation,
assertion indicates that the master is ready to accept data.
1.5.1.3.7
Parity (PCIPAR)
The PCIPAR signal indicates the parity of data on the PCIAD[31:0] and PCICXBE[3:0] lines.
1.5.1.3.8
Parity Error (PCIPERR)
The PCIPERR signal is asserted when a data phase parity error is detected if enabled.
1.5.1.3.9
Reset (PCIRESET)
The PCIRESET signal is asserted active low by MCF548x to reset the PCI bus. This signal is asserted after
the MCF548x is reset and must be negated to enable usage of the PCI bus.
相关PDF资料 |
PDF描述 |
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| MCF5484CZP200 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388 |
| MCF5485CVR200 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388 |
| MCF5483CVR166 | 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388 |
| MCF5481CZP166 | 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388 |
| MCF5484CVR200 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MCF5482 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor |
| MCF5482CVR166 | 功能描述:微处理器 - MPU MCF548X V4ECORE MMU FPU RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MCF5482CZP166 | 功能描述:微处理器 - MPU MCF548X V4ECORE MMU FPU RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MCF5483 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor |
| MCF5483CVR166 | 功能描述:微处理器 - MPU MCF548X V4ECORE MMU FPU RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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