参数资料
型号: MCF5481CZP166
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
封装: 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件页数: 5/96页
文件大小: 2006K
代理商: MCF5481CZP166
MOTOROLA
MCF548x Integrated Microprocessor Hardware Specifications
13
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MCF548x Family Features
logical step is to integrate a cryptography accelerator on an embedded processor, such as the MCF548x
family.
Motorola has developed the SEC on the MCF548x family for this purpose. This block accelerates the core
cryptography algorithms that underlie standard Internet security protocols like SSL/TLS, IPSec, IKE, and
WTLS/WAP.
The SEC includes execution units for the following:
— DES/3DES block cipher
— AES block cipher
— RC4 stream cipher
— MD5/SHA-1/SHA-256/HMAC hashing
— Random number generator compliant with FIPS 140-1 standards for randomness and
non-determinism
Dual-channel architecture permits single-pass encryption and authentication
1.4.11 System Integration Unit (SIU)
1.4.11.1 Timers
The MCF548x family integrates several timer functions required by most embedded systems. Two internal
32-bit slice timers are provided to create short cycle periodic interrupts, typically utilized for RTOS
scheduling and alarm functionality. A watchdog timer is included which will reset the processor if not
regularly serviced, catching software hang-ups. Four 32-bit general purpose timers are included, which are
capable of input capture, output compare, and PWM functionality.
1.4.11.2 Interrupt Controller
The interrupt controller on the MCF548x family can support up to 63 interrupt sources. The interrupt
controller is organized as seven levels with nine interrupt sources per level. Each interrupt source has a
unique interrupt vector, and 56 of the 63 sources of a given controller provide a programmable level [1-7]
and priority within the level.
Support for up to 63 interrupt sources organized as follows:
— 56 fully-programmable interrupt sources
— 7 fixed-level interrupt sources
Seven external interrupt signals
Unique vector number for each interrupt source
Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
Support for hardware and software interrupt acknowledge (IACK) cycles
Combinatorial path to provide wake-up from low power modes
1.4.11.3 General Purpose I/O
All peripheral I/O pins on the MCF548x family are muxed with GPIO, adding flexibility and usability to all
signals on the chip.
相关PDF资料
PDF描述
MCF5484CZP200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
MCF5485CVR200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
MCF5483CVR166 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
MCF5481CZP166 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388
MCF5484CVR200 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
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