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| 型号： | MCIMX31LCVKN5C |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 532 MHz, MICROPROCESSOR, PBGA457 |
| 封装： | 14 X 14 MM, 0.50 MM PITCH, ROHS COMPLIANT, MAPBGA-457 |
| 文件页数： | 87/122页 |
| 文件大小： | 1418K |
| 代理商： | MCIMX31LCVKN5C |
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Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
Freescale Semiconductor
67
4.3.15.4.2
Interface to a TV Encoder, Electrical Characteristics
The timing characteristics of the TV encoder interface are identical to the synchronous display
characteristics. See Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical
4.3.15.5
Asynchronous Interfaces
4.3.15.5.1
Parallel Interfaces, Functional Description
The IPU supports the following asynchronous parallel interfaces:
System 80 interface
— Type 1 (sampling with the chip select signal) with and without byte enable signals.
— Type 2 (sampling with the read and write signals) with and without byte enable signals.
System 68k interface
— Type 1 (sampling with the chip select signal) with or without byte enable signals.
— Type 2 (sampling with the read and write signals) with or without byte enable signals.
For each of four system interfaces, there are three burst modes:
1. Burst mode without a separate clock. The burst length is defined by the corresponding parameters
of the IDMAC (when data is transferred from the system memory) of by the HBURST signal (when
the MCU directly accesses the display via the slave AHB bus). For system 80 and system 68k type
1 interfaces, data is sampled by the CS signal and other control signals changes only when transfer
direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD signals
(system 80) or by the ENABLE signal (system 68k) and the CS signal stays active during the whole
burst.
2. Burst mode with the separate clock DISPB_BCLK. In this mode, data is sampled with the
DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are
changed simultaneously with data when the bus state (read, write or wait) is altered. The CS
signals and other controls move to non-active state after burst has been completed.
3. Single access mode. In this mode, slave AHB and DMA burst are broken to single accesses. The
data is sampled with CS or other controls according the interface type as described above. All
controls (including CS) become non-active for one display interface clock after each access. This
mode corresponds to the ATI single access mode.
Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 52,
DISPB_D#_WR and DISPB_D#_RD signals.
Additionally, the IPU allows a programmable pause between two burst. The pause is defined in the
HSP_CLK cycles. It allows to avoid timing violation between two sequential bursts or two accesses to
different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
相关PDF资料 |
PDF描述 |
|---|---|
| MCIMX31VMN5C | 532 MHz, MICROPROCESSOR, PBGA473 |
| MCIMX31CVKN5C | 532 MHz, MICROPROCESSOR, PBGA457 |
| MCIMX31CVKN5CR2 | 532 MHz, MICROPROCESSOR, PBGA457 |
| MCIMX31VKN5B | 532 MHz, MICROPROCESSOR, PBGA457 |
| MCIMX31LVKN5BR2 | 532 MHz, MICROPROCESSOR, PBGA457 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MCIMX31LCVKN5CR2 | 功能描述:IC MPU MAP I.MX31L 457-MAPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:i.MX31 标准包装:1 系列:AVR® ATmega 核心处理器:AVR 芯体尺寸:8-位 速度:16MHz 连通性:I²C，SPI，UART/USART 外围设备:欠压检测/复位，POR，PWM，WDT 输入/输出数:32 程序存储器容量:32KB（16K x 16） 程序存储器类型:闪存 EEPROM 大小:1K x 8 RAM 容量:2K x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 5.5 V 数据转换器:A/D 8x10b 振荡器型:内部 工作温度:-40°C ~ 125°C 封装/外壳:44-TQFP 包装:剪切带 (CT) 其它名称:ATMEGA324P-B15AZCT |
| MCIMX31LCVKN5D | 功能描述:处理器 - 专门应用 2.0.1 CONSUMER LITE RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MCIMX31LCVKN5DR2 | 功能描述:处理器 - 专门应用 2.0.1 CONSUMER LITE RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MCIMX31LCVMN4C | 功能描述:处理器 - 专门应用 TORTOLA MX31 AUTO FULL RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MCIMX31LCVMN4CR2 | 功能描述:处理器 - 专门应用 TORTOLA MX31 AUTO FULL RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
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