参数资料
型号: MCIMX53-START-R
厂商: Freescale Semiconductor
文件页数: 12/144页
文件大小: 0K
描述: KIT DEVELOPMENT I.MX53
标准包装: 1
系列: i.MX53
类型: MCU
适用于相关产品: i.MX53
所含物品:
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3. Specifications  
3.1. i.MX535   Processor  
The ? i.MX535 ? Applications ? Processor ? (AP) ? is ? based ? on ? ARM ? Cortex ‐ A8 TM ? Platform, ? which ? has ? the ? following ?
features: ?
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MMU, ? L1 ? Instruction ? and ? L1 ? Data ? Cache ?
Unified ? L2 ? cache ?
Target ? frequency ? of ? the ? core ? (including ? Neon, ? VFPv3 ? and ? L1 ? Cache): ? 1.0 ? GHz ?
Neon ? coprocessor ? (SIMD ? Media ? Processing ? Architecture) ? and ? Vector ? Floating ? Point ? (VFP ‐ Lite) ?
coprocessor ? supporting ? VFPv3 ?
TrustZone ?
The ? memory ? system ? consists ? of ? the ? following ? components: ?
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Level ? 1 ? Cache: ?
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Instruction ? (32 ? Kbyte) ?
Data ? (32 ? Kbyte) ?
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Level ? 2 ? Cache: ?
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Unified ? instruction ? and ? data ? (256 ? Kbyte) ?
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Level2 ? (internal) ? memory: ?
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Boot ? ROM, ? including ? HAB ? (64 ? Kbyte) ?
Internal ? multimedia/shared, ? fast ? access ? RAM ? (128 ? Kbyte) ?
Secure/non ‐ secure ? RAM ? (16 ? Kbyte) ?
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External ? memory ? interfaces: ?
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16/32 ‐ bit ? DDR2 ‐ 800, ? LV ‐ DDR2 ‐ 800 ? or ? DDR3 ‐ 800 ? up ? to ? 2 ? Gbyte ?
32 ? bit ? LPDDR2 ?
8/16 ‐ bit ? NAND ? SLC/MLC ? Flash, ? up ? to ? 66 ? MHz, ? 4/8/14/16 ‐ bit ? ECC ?
16 ‐ bit ? NOR ? Flash. ? All ? WEIMv2 ? pins ? are ? muxed ? on ? other ? interfaces ? (data ? with ? NFC ? pins). ?
I/O ? muxing ? logic ? selects ? WEIMv2 ? port, ? as ? primary ? muxing ? at ? system ? boot. ?
16 ‐ bit ? SRAM, ? cellular ? RAM ?
Samsung ? One ? NAND TM ? and ? managed ? NAND ? including ? eMMC ? up ? to ? rev ? 4.4 ? (in ? muxed ? I/O ?
mode) ?
The ? i.MX53 ? system ? is ? built ? around ? the ? following ? system ? on ? chip ? interfaces: ?
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64 ‐ bit ? AMBA ? AXI ? v1.0 ? bus ? – ? used ? by ? ARM ? platform, ? multimedia ? accelerators ? (such ? as ? VPU, ? IPU, ?
GPU3D, ? GPU2D) ? and ? the ? external ? memory ? controller ? (EXTMC) ? operating ? at ? 200 ? MHz. ?
32 ‐ bit ? AMBA ? AHB ? 2.0 ? bus ? – ? used ? by ? the ? rest ? of ? the ? bus ? master ? peripherals ? operating ? at ? 133 ?
MHz. ?
32 ‐ bit ? IP ? bus ? – ? peripheral ? bus ? used ? for ? control ? (and ? slow ? data ? traffic) ? of ? the ? most ? system ?
peripheral ? devices ? operating ? at ? 66 ? MHz. ?
The ? i.MX53 ? makes ? use ? of ? dedicated ? hardware ? accelerators ? to ? achieve ? state ‐ of ‐ the ‐ art ? multimedia ?
performance. ? The ? use ? of ? hardware ? accelerators ? provides ? both ? high ? performance ? and ? low ? power ?
consumption ? while ? freeing ? up ? the ? CPU ? core ? for ? other ? tasks. ?
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Freescale Semiconductor
Hardware User Guide for i.MX53 Quick Start Board,
Preliminary Rev 0.91
4
PUBI – Public Use Business Information ?
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MCIMX53-START-R 制造商:Freescale Semiconductor 功能描述:DEV KIT I.MX53 1GHZ ARM CORTEX A8 制造商:Freescale Semiconductor 功能描述:I.MX53, WITH PMIC, QUICK START BOARD 制造商:Freescale Semiconductor 功能描述:I.MX53, WITH PMIC, QUICK START BOARD; Silicon Manufacturer:Freescale; Core Architecture:ARM; Core Sub-Architecture:Cortex-A8; Silicon Core Number:i.MX53; Silicon Family Name:i.MX53; Kit Contents:Processor, PMIC, microSD, Power ;RoHS Compliant: No
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