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参数资料
| 型号： | MCM69F536CTQ8.5 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | SRAM |
| 英文描述： | 32K X 36 CACHE SRAM, 8.5 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 11/12页 |
| 文件大小： | 355K |
| 代理商： | MCM69F536CTQ8.5 |
MCM69F536C
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . . . .
Input Pulse Levels
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
1 V/ns (20% to 80%)
. . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Load
See Figure 1 Unless Otherwise Noted
. . . . . . . . . . . . . .
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
P
Sb l
–7.5
–8
–8.5
–9
–10
–12
Ui
N
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
12
—
12
—
12
—
12
—
15
—
16.6
—
ns
Clock High Pulse
Width
tKHKL
4
—
4
—
4
—
4
—
5
—
6
—
ns
Clock Low Pulse
Width
tKLKH
4
—
4
—
4
—
4
—
5
—
6
—
ns
Clock Access
Time
tKHQV
—
7.5
—
8
—
8.5
—
9
—
10
—
12
ns
Output Enable to
Output Valid
tGLQV
—
5
—
5
—
5
—
5
—
5
—
6
ns
Clock High to
Output Active
tKHQX1
0
—
0
—
0
—
0
—
0
—
0
—
ns
4
Clock High to
Output Change
tKHQX2
3
—
3
—
3
—
3
—
3
—
3
—
ns
4
Output Enable to
Output Active
tGLQX
0
—
0
—
0
—
0
—
0
—
0
—
ns
4
Output Disable to
Q High–Z
tGHQZ
—
5
—
5
—
5
—
5
—
5
—
6
ns
4, 5
Clock High to Q
High–Z
tKHQZ
2.5
5
2.5
5
2.5
5
3
5
3
5
3
6
ns
4, 5
Setup Times:
Address
ADSP, ADSC,
ADV
Data In
Write
Chip Enable
tADKH
tADSKH
tDVKH
tWVKH
tEVKH
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
ns
Hold Times:
Address
ADSP, ADSC,
ADV
Data In
Write
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHEX
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
4. This parameter is sampled and not 100% tested.
5. Measured at
± 200 mV from steady state.
OUTPUT
Z0 = 50
RL = 50
VT = 1.5 V
Figure 1. AC Test Load
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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