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| 型号： | MCP1623T-I/MC |
| 厂商： | Microchip Technology |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | IC BOOST SYNC REG PWM 8DFN |
| 标准包装： | 3,300 |
| 应用： | 转换器，PIC? 微控制器 |
| 输入电压： | 0.8 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 2 V ~ 5.5 V |
| 工作温度： | -45°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-VFDFN 裸露焊盘 |
| 供应商设备封装： | 8-DFN（2x3） |
| 包装： | 带卷 (TR) |
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MCP1623/24
3.0
PIN DESCRIPTIONS
TABLE 3-1:
PIN FUNCTION TABLE
MCP1623/24
Pin Name
SOT23
2x3 DFN
Description
SW
GND
EN
FB
V OUT
V IN
S GND
P GND
V OUTS
V OUTP
EP
1
2
3
4
5
6
—
—
—
—
—
5
—
4
1
—
8
2
3
7
6
9
Switch Node, Boost Inductor Input Pin
Ground Pin
Enable Control Input Pin
Feedback Voltage Pin
Output Voltage Pin
Input Voltage Pin
Signal Ground Pin
Power Ground Pin
Output Voltage Sense Pin
Output Voltage Power Pin
Exposed Thermal Pad (EP); must be connected to V SS.
3.1
Switch Node Pin (SW)
3.6
Power Supply Input Voltage Pin
Connect the inductor from the input voltage to the SW
pin. The SW pin carries inductor current and can be as
high as 425 mA peak. The integrated N-Channel switch
drain and integrated P-Channel switch source are
(V IN )
Connect the input voltage source to V IN . The input
source should be decoupled to GND with a 4.7 μF
minimum capacitor.
internally connected at the SW node.
3.7
Signal Ground Pin (S GND )
3.2
Ground Pin (GND)
The signal ground pin is used as a return for the
integrated V REF and error amplifier. In the 2x3 DFN
The ground or return pin is used for circuit ground
connection. Length of trace from input cap return, output
cap return and GND pin should be made as short as
possible to minimize noise on the GND pin.
package, the S GND and power ground (P GND ) pins are
connected externally.
3.8 Power Ground Pin (P GND )
The power ground pin is used as a return for the high--
3.3
Enable Pin (EN)
current N-Channel switch. In the 2x3 DFN package, the
P GND and signal ground (S GND ) pins are connected
The EN pin is a logic-level input used to enable or
externally.
disable device switching and lower quiescent current
while disabled. A logic high (>90% of V IN ) will enable
3.9
Output Voltage Sense Pin (V OUTS )
the regulator output. A logic low (<20% of V IN ) will
ensure that the regulator is disabled.
The output voltage sense pin connects the regulated
output voltage to the internal bias circuits. In the 2x3
DFN package, V OUTS and V OUTP are connected
3.4
Feedback Voltage Pin (FB)
externally.
The FB pin is used to provide output voltage regulation
3.10
Output Voltage Power Pin (V OUTP )
by using a resistor divider. The FB voltage will be 1.21V
typical with the output voltage in regulation.
3.5 Output Voltage Pin (V OUT )
The output voltage pin connects the integrated
P-Channel MOSFET to the output capacitor. The FB
voltage divider is also connected to the V OUT pin for
voltage regulation.
? 2011 Microchip Technology Inc.
The output voltage power pin connects the output
voltage to the switch node. High current flows through
the integrated P-Channel and out of this pin to the
output capacitor and output. In the 2x3 DFN package,
V OUTS and V OUTP are connected externally.
3.11 Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the V SS pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
DS41420C-page 9
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