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参数资料
| 型号： | MCP1650S-E/MS |
| 厂商： | Microchip Technology |
| 文件页数： | 20/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST FLYBK PWM 8MSOP |
| 标准包装： | 100 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 850kHz |
| 占空比： | 80% |
| 电源电压： | 2.7 V ~ 5.5 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 包装： | 管件 |
| 产品目录页面： | 668 (CN2011-ZH PDF) |
| 配用： | MCP1650EV-ND - BOARD EVAL FOR MCP1650,51,52,53 MCP1650DM-LED1-ND - BOARD DEMO FOR MCP165X |
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MCP1650/51/52/53
6.0
TYPICAL LAYOUT
MCP1651R
(+2.8V to +4.8V Input to +5V Output @ 1A)
Coilcraft
L1
R2
49.9K
8 V
3
2 1
EXT
GND
FB
LBI
/LBO
/SHDN
PGND
TP5
Q1
IRLML2502
+5V Output @ 1A
R4
0.1
LED Low Input
TP1
+V IN _1
F1
FUSE
Single-Cell Li-Ion
Input (2.8V to 4.8V)
TP4
GND
?
DO1813HC
2A Power Train Path
3.3 μH
R1
C2 100
47μ
IN CS
C3
R5 0.1μ 6 4
73.2K 5 7
0 0
AGND AGND
0 MCP1651_MSOP
R8
49.9K
/SHDN1
0
AGND
0
PGND
D1
B330ADIC VR
R3
3.09K
R6
1K
0
AGND
R7
562
D2
TP2
+V OUT _1
VR
C1
47μ
TP3
GND
0
PGND
Keep Away From Switching Section
FIGURE 6-1:
MCP1650/51/52/53 Application Schematic.
flow will quickly change to +V IN _1 to F 1 to L 1 to D 1 to
When designing the physical layout for the MCP1650/
51/52/53, the highest priority should be placing the
boost power train components in order to minimize the
size of the high current paths. It is also important to pro-
vide ground-path separation between the large-signal
power train ground and the small signal feedback path
and feature grounds. In some cases, additional filtering
on the V IN pin is helpful to minimize MCP1650/51/52/53
input noise.
In this layout example, the critical power train paths are
from input to output, +V IN _1 to F 1 to C 2 to L 1 to Q 1 to
GND. Current will flow in this path when the switch (Q 1 )
is turned on. When Q 1 is turned off, the path for current
C 1 to R4 to GND. When starting the layout for this appli-
cation, both of these power train paths should be as
short as possible. The C 2 , Q 1 and R 4 GND connections
should all be connected to a single “Power Ground”
plane to minimize any wiring inductance.
Bold traces are used to represent high-current
connections and should be made as wide as is
practical.
R 1 and C 3 is an optional filter that reduces the
switching noise on the V IN pin of the MCP1650/51/52/
53. This should be considered for high-power
applications (> 1W) and bootstrap applications where
V IN of the MCP1650/51/52/53 is supplied by the output
voltage of the boost regulator.
DS21876A-page 20
The feedback resistor divider that sets the output
voltage should be considered sensitive and be routed
away from the power-switching components discussed
previously.
As shown in the diagram, R 6 , R 8 and the GND pin of
the MCP1650/51/52/53 should be returned to an
analog ground plane.
The analog ground plane and power ground plane
should be connected at a single point close to the input
capacitor (C 2 ).
? 2004 Microchip Technology Inc.
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