参数资料
型号: MCP1827-2502E/AT
厂商: Microchip Technology
文件页数: 15/32页
文件大小: 0K
描述: IC REG LDO 2.5V 1.5A TO220-5
产品培训模块: High Current LDOs
标准包装: 50
稳压器拓扑结构: 正,固定式
输出电压: 2.5V
输入电压: 最高 6V
电压 - 压降(标准): 0.33V @ 1.5A
稳压器数量: 1
电流 - 输出: 1.5A(最小)
工作温度: -40°C ~ 125°C
安装类型: 通孔
封装/外壳: TO-220-5
供应商设备封装: TO-220-5
包装: 管件
产品目录页面: 667 (CN2011-ZH PDF)
MCP1827/MCP1827S
3.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
3-Pin Fixed
Output
1
2
3
Pad
5-Pin Fixed
Output
1
2
3
4
5
Pad
Adjustable
Output
1
2
3
4
5
Pad
Name
SHDN
V IN
GND
V OUT
PWRGD
ADJ
EP
Description
Shutdown Control Input (active-low)
Input Voltage Supply
Ground
Regulated Output Voltage
Power Good Output
Voltage Adjust/Sense Input
Exposed Pad of the Package (ground potential)
3.1
Input Voltage Supply (V IN )
3.4
Power Good Output (PWRGD)
Connect the unregulated or regulated input voltage
source to V IN . If the input voltage source is located
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 μF to
10 μF should be sufficient for most applications.
The PWRGD output is an open-drain output used to
indicate when the LDO output voltage is within 92%
(typically) of its nominal regulation value. The PWRGD
threshold has a typical hysteresis value of 2%. The
PWRGD output is delayed by 200 μs (typical) from the
time the LDO output is within 92% + 3% (max
hysteresis) of the regulated output value on power-up.
3.2
Shutdown Control Input (SHDN)
This delay time is internally fixed.
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
3.5
Output Voltage Adjust Input (ADJ)
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typical quiescent current is 0.1 μA.
For adjustable applications, the output voltage is
connected to the ADJ input through a resistor divider
that sets the output voltage regulation value. This
provides the user the capability to set the output
voltage to any value they desire within the 0.8V to 5.0V
range of the device.
3.3
Ground (GND)
3.6
Regulated Output Voltage (V OUT )
Connect the GND pin of the LDO to a quiet circuit
ground. This will help the LDO power supply rejection
ratio and noise performance. The ground pin of the
LDO only conducts the quiescent current of the LDO
(typically 120 μA), so a heavy trace is not required.
For applications have switching or noisy inputs tie the
The V OUT pin is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 μF is
required for LDO stability. The MCP1827/MCP1827S is
stable with ceramic, tantalum and aluminum-electro-
lytic capacitors. See Section 4.3 “Output Capacitor”
for output capacitor selection guidance.
GND pin to the return of the output capacitor. Ground
planes help lower inductance and voltage spikes
3.7
Exposed Pad (EP)
caused by fast transient load currents and are
recommended for applications that are subjected to
fast load transients.
? 2007 Microchip Technology Inc.
The DDPAK and TO-220 package have an exposed tab
on the package. A heat sink may be mount to the tab to
aid in the removal of heat from the package during
operation. The exposed tab is at the ground potential of
the LDO.
DS22001C-page 15
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