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| 型号： | MCP2150-I/SS |
| 厂商： | Microchip Technology |
| 文件页数： | 52/52页 |
| 文件大小： | 0K |
| 描述： | IC IRDA STD CONTROLLER 20SSOP |
| 产品培训模块： | IrDA® Standard Protocol |
| 标准包装： | 67 |
| 控制器类型： | IRDA 标准协议栈控制器 |
| 接口： | UART |
| 电源电压： | 3 V ~ 5.5 V |
| 电流 - 电源： | 7mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 管件 |
| 产品目录页面： | 685 (CN2011-ZH PDF) |
| 配用： | MCP215XDM-ND - BOARD DEMO FOR MCP215X |
| 其它名称： | MCP2150I/SS |
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2002 Microchip Technology Inc.
Preliminary
DS21655B-page 9
MCP2150
2.6
Modulation
The data that the MCP2150 UART received (on the TX
pin) that needs to be transmitted (on the TXIR pin) will
need to be modulated. This modulated signal drives the
IR transceiver module. Figure 2-3 shows the encoding
of the modulated signal.
Each bit time is comprised of 16-bit clocks. If the value
to be transmitted (as determined by the TX pin) is a
logic low, then the TXIR pin will output a low level for
7-bit clock cycles, a logic high level for 3-bit clock
cycles or a minimum of 1.6 sec. (see parameter
IR121). The remaining 6-bit clock cycles will be low. If
the value to transmit is a logic high, then the TXIR pin
will output a low level for the entire 16-bit clock cycles.
2.7
Demodulation
The modulated signal (data) from the IR transceiver
module (on RXIR pin) needs to be demodulated to form
the received data (on RX pin). Once demodulation of
the data byte occurs, the data that is received is trans-
mitted by the MCP2150 UART (on the RX pin).
Figure 2-4 shows the decoding of the modulated
signal.
Each bit time is comprised of 16-bit clocks. If the value
to be received is a logic low, then the RXIR pin will be
a low level for the first 3-bit clock cycles or a minimum
of 1.6 s. The remaining 13-bit clock cycles (or differ-
ence up to the 16-bit clock time) will be high. If the value
to be received is a logic high, then the RXIR pin will be
a high level for the entire 16-bit clock cycles. The level
on the RX pin will be in the appropriate state for the
entire 16 clock cycles.
FIGURE 2-3:
ENCODING
FIGURE 2-4:
DECODING
Note:
The signal on the TXIR pin does not actu-
ally line up in time with the bit value that
was transmitted on the TX pin, as shown in
Figure 2-3. The TX bit value is shown to
represent the value to be transmitted on
the TXIR pin.
Note:
The signal on the RX pin does not actually
line up in time with the bit value that was
received on the RXIR pin, as shown in
Figure 2-4. The RXIR bit value is shown to
represent the value to be transmitted on
the RX pin.
BITCLK
TX Bit
TXIR
01
0
1
16 CLK
7 CLK
Start Bit
Data bit 0
Data bit 1
Data bit 2
Data bit ...
24 Tosc
Value
BITCLK
RX
RXIR Bit
01
0
1
≥ 1.6 s (up to 3 CLK)
≥ 13 CLK
16 CLK
Start Bit
Data bit 0
Data bit 1
Data bit 2
Data bit ...
(CLK)
Value
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