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| 型号： | MCP2515DM-PCTL |
| 厂商： | Microchip Technology |
| 文件页数： | 6/92页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO FOR MCP2515 |
| 标准包装： | 1 |
| 系列： | PICtail™ |
| 主要目的： | 接口，CAN 控制器 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | MCP2515，MCP25020 |
| 主要属性： | 带 CAN 输入/输出扩展器的独立 CAN 控制器 |
| 已供物品： | 板，缆线，CD |
| 产品目录页面： | 685 (CN2011-ZH PDF) |
| 相关产品： | MCP2515T-I/ST-ND - IC CAN CONTROLLER W/SPI 20TSSOP MCP2515T-I/SO-ND - IC CAN CONTROLLER W/SPI 18SOIC MCP2515T-E/ST-ND - IC CAN CONTROLLER W/SPI 20TSSOP MCP2515T-E/SO-ND - IC CAN CONTROLLER W/SPI 18SOIC MCP2515-E/ST-ND - IC CAN CONTROLLER W/SPI 20TSSOP MCP2515-E/SO-ND - IC CAN CONTROLLER W/SPI 18SOIC MCP2515-E/P-ND - IC CAN CONTROLLER W/SPI 18DIP MCP2515-I/ST-ND - IC CAN CONTROLLER W/SPI 20TSSOP MCP2515-I/SO-ND - IC CAN CONTROLLER W/SPI 18SOIC MCP2515-I/P-ND - IC CAN CONTROLLER W/SPI 18DIP 更多... |
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MCP2515
1.5
CAN Protocol Engine
1.5.3
ERROR MANAGEMENT LOGIC
The CAN protocol engine combines several functional
blocks, shown in Figure 1-4 and described below.
The Error Management Logic (EML) is responsible for
the fault confinement of the CAN device. Its two
counters, the Receive Error Counter (REC) and the
1.5.1
PROTOCOL FINITE STATE
Transmit Error Counter (TEC), are incremented and
MACHINE
The heart of the engine is the Finite State Machine
(FSM). The FSM is a sequencer that controls the
sequential data stream between the TX/RX shift
decremented by commands from the bit stream
processor. Based on the values of the error counters,
the CAN controller is set into the states error-active,
error-passive or bus-off.
register, the CRC register and the bus line. The FSM
also controls the Error Management Logic (EML) and
1.5.4
BIT TIMING LOGIC
the parallel data stream between the TX/RX shift
registers and the buffers. The FSM ensures that the
processes of reception, arbitration, transmission and
error-signaling are performed according to the CAN
protocol. The automatic retransmission of messages
on the bus line is also handled by the FSM.
The Bit Timing Logic (BTL) monitors the bus line input
and handles the bus-related bit timing according to the
CAN protocol. The BTL synchronizes on a recessive-
to-dominant bus transition at Start-of-Frame (hard
synchronization) and on any further recessive-to-
dominant bus line transition if the CAN controller itself
does not transmit a dominant bit (resynchronization).
1.5.2
CYCLIC REDUNDANCY CHECK
The BTL also provides programmable time segments
The Cyclic Redundancy Check register generates the
Cyclic Redundancy Check (CRC) code, which is
transmitted after either the Control Field (for messages
with 0 data bytes) or the Data Field and is used to
check the CRC field of incoming messages.
to compensate for the propagation delay time, phase
shifts and to define the position of the sample point
within the bit time. The programming of the BTL
depends on the baud rate and external physical delay
times.
FIGURE 1-4:
CAN PROTOCOL ENGINE BLOCK DIAGRAM
RX
Bit Timing Logic
Transmit Logic
TX
SAM
Sample<2:0>
Receive
REC
Error Counter
TEC
StuffReg<5:0>
Majority
Decision
BusMon
Comparator
CRC<14:0>
Comparator
Shift<14:0>
(Transmit<5:0>, Receive<7:0>)
Transmit
Error Counter
Protocol
FSM
ErrPas
BusOff
SOF
Receive<7:0>
RecData<7:0>
Transmit<7:0>
TrmData<7:0>
DS21801G-page 6
Interface to Standard Buffer
Rec/Trm Addr.
? 2003-2012 Microchip Technology Inc.
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