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| 型号： | MCP2515T-I/SO |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDSO18 |
| 封装： | 7.50 MM, LEAD FREE, PLASTIC, SOIC-18 |
| 文件页数： | 56/88页 |
| 文件大小： | 1205K |
| 代理商： | MCP2515T-I/SO |
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MCP2515
DS21801F-page 6
2010 Microchip Technology Inc.
1.5
CAN Protocol Engine
The CAN protocol engine combines several functional
blocks, shown in Figure 1-4 and described below.
1.5.1
PROTOCOL FINITE STATE
MACHINE
The heart of the engine is the Finite State Machine
(FSM). The FSM is a sequencer that controls the
sequential data stream between the TX/RX shift
register, the CRC register and the bus line. The FSM
also controls the Error Management Logic (EML) and
the parallel data stream between the TX/RX shift
registers and the buffers. The FSM ensures that the
processes of reception, arbitration, transmission and
error-signaling are performed according to the CAN
protocol. The automatic retransmission of messages
on the bus line is also handled by the FSM.
1.5.2
CYCLIC REDUNDANCY CHECK
The Cyclic Redundancy Check register generates the
Cyclic Redundancy Check (CRC) code, which is
transmitted after either the Control Field (for messages
with 0 data bytes) or the Data Field and is used to
check the CRC field of incoming messages.
1.5.3
ERROR MANAGEMENT LOGIC
The Error Management Logic (EML) is responsible for
the fault confinement of the CAN device. Its two
counters, the Receive Error Counter (REC) and the
Transmit Error Counter (TEC), are incremented and
decremented by commands from the bit stream
processor. Based on the values of the error counters,
the CAN controller is set into the states error-active,
error-passive or bus-off.
1.5.4
BIT TIMING LOGIC
The Bit Timing Logic (BTL) monitors the bus line input
and handles the bus-related bit timing according to the
CAN protocol. The BTL synchronizes on a recessive-
to-dominant bus transition at Start-of-Frame (hard
synchronization) and on any further recessive-to-
dominant bus line transition if the CAN controller itself
does not transmit a dominant bit (resynchronization).
The BTL also provides programmable time segments
to compensate for the propagation delay time, phase
shifts and to define the position of the sample point
within the bit time. The programming of the BTL
depends on the baud rate and external physical delay
times.
FIGURE 1-4:
CAN PROTOCOL ENGINE BLOCK DIAGRAM
Bit Timing Logic
CRC<14:0>
Comparator
Receive<7:0>
Transmit<7:0>
Sample<2:0>
Majority
Decision
StuffReg<5:0>
Comparator
Transmit Logic
Receive
Error Counter
Transmit
Error Counter
Protocol
FSM
RX
SAM
BusMon
Rec/Trm Addr.
RecData<7:0>
TrmData<7:0>
Shift<14:0>
(Transmit<5:0>, Receive<7:0>)
TX
REC
TEC
ErrPas
BusOff
Interface to Standard Buffer
SOF
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| MCP2515-E/ST | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDSO20 |
| MCP2515T-E/ST | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDSO20 |
| MCP2515T-E/ML | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC20 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MCP2551 | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Speed CAN Transceiver |
| MCP2551_07 | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Speed CAN Transceiver |
| MCP2551_10 | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Speed CAN Transceiver |
| MCP2551A-E/P | 功能描述:CAN 接口集成电路 Enhanced HI SPD CAN Transceiver RoHS:否 制造商:Texas Instruments 类型:Transceivers 工作电源电压:5 V 电源电流: 工作温度范围:- 40 C to + 85 C 封装 / 箱体:SOIC-8 封装:Tube |
| MCP2551A-E/SN | 功能描述:CAN 接口集成电路 Enhanced HI SPD CAN Transceiver RoHS:否 制造商:Texas Instruments 类型:Transceivers 工作电源电压:5 V 电源电流: 工作温度范围:- 40 C to + 85 C 封装 / 箱体:SOIC-8 封装:Tube |
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