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参数资料
| 型号： | MCP3021A4T-E/OT |
| 厂商： | Microchip Technology |
| 文件页数： | 9/26页 |
| 文件大小： | 0K |
| 描述： | ADC 10BIT I2C INTERFACE SOT23-5 |
| 标准包装： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 22.3k |
| 数据接口： | I²C，串行 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SC-74A，SOT-753 |
| 供应商设备封装： | SOT-23-5 |
| 包装： | 标准包装 |
| 输入数目和类型： | 1 个单端，单极 |
| 其它名称： | MCP3021A4T-E/OTDKR |
2003 Microchip Technology Inc.
DS21805A-page 17
MCP3021
The input signal will initially be sampled with the first
falling edge of the clock following the transmission of a
logic-high R/W bit. Additionally, with the rising edge of
the SCL, the ADC will transmit an acknowledge bit
(ACK = 0). The master must release the data bus dur-
ing this clock pulse to allow the MCP3021 to pull the
line low (refer to Figure 5-3).
For consecutive samples, sampling begins on the last
bit of the lower data byte. Refer to Figure 5-6 for timing
diagram.
5.3.2
READING THE CONVERSION DATA
After the MCP3021 acknowledges the address byte,
the device will transmit four ‘0’ bits followed by the
upper four data bits of the conversion. The master
device will then acknowledge this byte with an
ACK = low. With the following six clock pulses, the
MCP3021 will transmit the lower six data bits from the
conversion. The last two bits are “don’t cares”, and do
not contain valid data. The master then sends an
ACK = high, indicating to the MCP3021 that no more
data is requested. The master can then send a stop bit
to end the transmission.
FIGURE 5-5:
Executing a Conversion.
5.3.3
CONSECUTIVE CONVERSIONS
For consecutive samples, sampling begins on the fall-
ing edge of the last bit of the lower data byte. See
Figure 5-6 for timing.
FIGURE 5-6:
Continuous Conversion.
SDA
S
T
A
R
T
S
T
O
P
A
C
K
tACQ + tCONV is
initiated here
Address Byte
Address bits
Device bits
1 001 A
R/
W
Upper Data Byte
000 0 DD D
A
C
K
Lower Data Byte
N
A
K
S
P
9 8
2
A
1
A
0
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0X X
123 456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SCL
SDA
fSAMP = 22.3 ksps (fCLK = 400 kHz)
A
C
K
tACQ + tCONV is
initiated here
Address Byte
Address bits
Device bits
100 1 A2 A1 A0
R
/
W
Upper Data Byte (n)
A
C
K
Lower Data Byte (n)
A
C
K
S
tACQ + tCONV is
initiated here
00 0 0 D DD
98 7
D
6
D
5
D
4
D
3
D
2
D
1
D
0X X
123 456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SCL
S
T
A
R
T
0
28
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