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参数资料
| 型号： | MCP3201-CI/P |
| 厂商： | Microchip Technology |
| 文件页数： | 14/40页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SINGLE CHAN 8DIP |
| 标准包装： | 60 |
| 位数： | 12 |
| 采样率（每秒）： | 100k |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个单端，单极 |
| 产品目录页面： | 672 (CN2011-ZH PDF) |
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1998-2011 Microchip Technology Inc.
DS21290F-page 21
MCP3201
6.0
APPLICATIONS INFORMATION
6.1
Using the MCP3201 Device with
Microcontroller SPI Ports
With most microcontroller SPI ports, it is required to
clock out eight bits at a time. If this is the case, it will be
necessary to provide more clocks than are required for
the MCP3201. As an example, Figure 6-1 and
Figure 6-2 show how the MCP3201 device can be
interfaced to a microcontroller with a standard SPI port.
Since the MCP3201 always clocks data out on the
falling edge of clock, the MCU SPI port must be
configured to match this operation. SPI Mode 0,0 (clock
idles low) and SPI Mode 1,1 (clock idles high) are both
compatible with the MCP3201. Figure 6-1 depicts the
operation shown in SPI Mode 0,0, which requires that
the CLK from the microcontroller idles in the ‘low’ state.
As shown in the diagram, the MSB is clocked out of the
A/D Converter on the falling edge of the third clock
pulse. After the first eight clocks have been sent to the
device, the microcontroller’s receive buffer will contain
two unknown bits (the output is at high-impedance for
the first two clocks), the null bit and the highest order
five bits of the conversion. After the second eight clocks
have been sent to the device, the MCU receive register
will contain the lowest-order seven bits and the B1 bit
repeated as the A/D Converter has begun to shift out
LSB first data with the extra clock. Typical procedure
would then call for the lower-order byte of data to be
shifted right by one bit to remove the extra B1 bit. The
B7 bit is then transferred from the high-order byte to the
lower-order byte, and then the higher-order byte is
shifted one bit to the right as well. Easier manipulation
of the converted data can be obtained by using this
method.
Figure 6-2 shows the same thing in SPI Mode 1,1
which requires that the clock idles in the high state. As
with mode 0,0, the A/D Converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D Converter in on the rising edge of the clock.
FIGURE 6-1:
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
FIGURE 6-2:
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
CS
CLK
9
10
11
1213
1415
16
DOUT
NULL
BIT B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
HI-Z
B7
B6 B5 B4 B3 B2 B1 B0
B11 B10 B9
B8
??
0
MCU latches data from A/D
Data is clocked out of A/D
Converter on falling edges
Converter on rising edges of SCLK
123
4
5
6
7
8
HI-Z
B1
LSB first data begins
to come out
B2
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits
CS
CLK
9
101112
13
14
15
16
DOUT
NULL
BIT
B11 B10 B9
B8
B7
B6 B5 B4 B3 B2 B1 B0
HI-Z
B7
B6 B5 B4 B3 B2 B1 B0
B11 B10 B9
B8
??
0
MCU latches data from A/D
Data is clocked out of A/D
Converter on falling edges
Converter on rising edges of SCLK
12
3
4
56
7
8
B1
LSB first data begins
to come out
HI-Z
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits
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