参数资料
型号: MCP4532T-103E/MS
厂商: Microchip Technology
文件页数: 42/88页
文件大小: 0K
描述: IC POT DGTL 10K SGL 8-MSOP
标准包装: 2,500
接片: 129
电阻(欧姆): 10k
电路数: 1
温度系数: 标准值 150 ppm/°C
存储器类型: 易失
接口: I²C(设备位址)
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 带卷 (TR)
2008 Microchip Technology Inc.
DS22096A-page 47
MCP453X/455X/463X/465X
6.2.1.4
Repeated Start Bit
The Repeated Start bit (see Figure 6-5) indicates the
current Master Device wishes to continue communicat-
ing with the current Slave Device without releasing the
I2C bus. The Repeated Start condition is the same as
the Start condition, except that the Repeated Start bit
follows a Start bit (with the Data bits + A bit) and not a
Stop bit.
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is “High”.
FIGURE 6-5:
Repeat Start Condition
Waveform.
6.2.1.5
Stop Bit
The Stop bit (see Figure 6-6) Indicates the end of the
I2C Data Transfer Sequence. The Stop bit is defined as
the SDA signal rising when the SCL signal is “High”.
A Stop bit resets the I2C interface of all MCP4XXX
devices.
FIGURE 6-6:
Stop Condition Receive or
Transmit Mode.
6.2.2
CLOCK STRETCHING
“Clock Stretching” is something that the receiving
Device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP4XXX will not strech the clock signal (SCL)
since memory read acceses occur fast enough.
6.2.3
ABORTING A TRANSMISSION
If any part of the I2C transmission does not meet the
command format, it is aborted. This can be intentionally
accomplished with a START or STOP condition. This is
done so that noisy transmissions (usually an extra
START or STOP condition) are aborted before they
corrupt the device.
FIGURE 6-7:
Typical 8-Bit I2C Waveform Format.
FIGURE 6-8:
I2C Data States and Bit Sequence.
Note 1: A bus collision during the Repeated Start
condition occurs if:
SDA is sampled low when SCL goes
from low to high.
SCL goes low before SDA is asserted
low. This may indicate that another
master is attempting to transmit a
data "1".
SDA
SCL
Sr = Repeated Start
1st Bit
SCL
SDA A / A
P
1st Bit
SDA
SCL
S
2nd Bit
3rd Bit
4th Bit
5th Bit
6th Bit
7th Bit
8th Bit
P
A / A
SCL
SDA
START
Condition
STOP
Condition
Data allowed
to change
Data or
A valid
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