参数资料
型号: MCZ33927EK
厂商: Freescale Semiconductor
文件页数: 23/44页
文件大小: 0K
描述: IC FET PRE-DRIVER 3PH 54-SOIC
标准包装: 26
配置: 3 相桥
输入类型: 反相和非反相
延迟时间: 265ns
电流 - 峰: 600mA
配置数: 1
输出数: 3
高端电压 - 最大(自引导启动): 75V
电源电压: 8 V ~ 40 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 54-BSSOP(0.295",7.50mm 宽)裸露焊盘
供应商设备封装: 54-SOICW-EP
包装: 管件
FUNCTIONAL DESCRIPTIONS
INTRODUCTION
VLS REGULATOR (VLS)
VLS is the gate drive power supply regulated at
approximately 15V. This is an internally generated supply
from VPWR. It is the source for the low side gate drive
voltage, and also the high side bootstrap source. A low ESR
decoupling capacitor, capable of sourcing the pulsed drive
currents, must be connected between this pin and VSS or
PGND.
VPWR INPUT (VPWR)
VPWR is the power supply input for VLS and VDD. Current
flowing into this input recharges the bootstrap capacitors as
well as supplying power to the low-side gate drivers and the
VDD regulator. An internal regulator regulates the actual gate
voltages. This pin can be connected to system battery
voltage if power dissipation is not a concern.
EXPOSED PAD (EP)
The primary function of the Exposed Pad is to conduct
heat out of the device. This pad may be connected electrically
to the substrate of the device.The device will perform as
specified with the Exposed Pad un-terminated (floating).
However, it is recommended that the Exposed Pad be
terminated to pin 29 (VSS) and the system ground.
33927
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
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