参数资料
型号: MCZ33937AEK
厂商: Freescale Semiconductor
文件页数: 8/48页
文件大小: 0K
描述: IC PRE-DRIVER 3PH ENH 54-SOIC
标准包装: 26
系列: SMARTMOS™
配置: 3 相桥
输入类型: 非反相
延迟时间: 265ns
电流 - 峰: 600mA
配置数: 1
输出数: 3
高端电压 - 最大(自引导启动): 15V
电源电压: 8 V ~ 40 V
工作温度: -40°C ~ 135°C
安装类型: 表面贴装
封装/外壳: 54-BSSOP(0.295",7.50mm 宽)裸露焊盘
供应商设备封装: 54-SOICW-EP
包装: 管件
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 8.0 V ? V PWR = V SUP ? 40 V ?? -40 ? C ? T A ? 135 ? C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T A = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUTS
VPWR Supply Voltage Startup Threshold (9)
V PWR_ST
6.0
8.0
V
VSUP Supply Current, V PWR = V SUP = 40 V
RST and ENABLE = 5.0 V
I SUP
mA
No output loads on Gate Drive Pins, No PWM
No output loads on Gate Drive Pins, 20 kHz, 50% Duty Cycle
VPWR Supply Current, V PWR = V SUP = 40 V
I PWR_ON
1.0
10
mA
RST and ENABLE = 5.0 V
No output loads on Gate Drive Pins, No PWM, Outputs initialized
Output Loads = 620 nC per FET, 20 kHz PWM (10)
Sleep State Supply Current, RST = 0 V
11
20
95
μA
V SUP = 40 V
V PWR = 40 V
Sleep State Output Gate Voltage
IG < 100 μA
Trickle Charge Pump (Bootstrap Voltage) (14)
V SUP = 14 V
I SUP
I PWR
V GATESS
V Boot
22
14
56
28
30
100
1.3
32
V
V
Bootstrap Diode Forward Voltage at 10 mA
V F
1.2
V
VDD INTERNAL REGULATOR
V DD Output Voltage, V PWR = 8 to 40 V, C = 0.47 μF (11)
V DD
V
External Load I DD_EXT = 0 to 1.0 mA
4.5
5.5
Internal V DD Supply Current, V DD = 5.5 V, No External Load
I DD
12
mA
VLS REGULATOR
Peak Output Current, V PWR = 16 V, V LS = 10 V
I PEAK
350
600
800
mA
Linear Regulator Output Voltage, I VLS = 0 to 60 mA,V PWR > V LS + 2.0
VLS Disable Threshold (13)
V (12)
V LS
V THVLS
13.5
7.5
15
8.0
17
8.5
V
V
Notes
9. Operation with the Charge Pump is recommended when minimum system voltage could be less than 14 V. V PWR must exceed this
threshold in order for the Charge Pump and V DD regulator to startup and drive V PWR to > 8.0 V. Once V PWR exceeds 8.0 V, the circuits
will continue to operate even if system voltage drops below 6.0 V.
10. This parameter is guaranteed by design. It is not production tested.
11. Minimum external capacitor for stable V DD operation is 0.47 μF.
12.
13.
14.
Recommended external capacitor for the V LS regulator is 2.2 μF low ESR at each pin VLS and VLS_CAP.
When V LS is less than this value, the outputs are disabled and HOLDOFF circuits are active. Recovery requires initialization when V LS
rises above this threshold again. A filter delay of approximately 700 ns on the comparator output eliminates responses to spurious
transients on V LS .
See Figure 11 for typical capability to maintain gate voltage with a 5.0 μA load.
33937A
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
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