153
8011Q–AVR–02/2013
ATmega164P/324P/644P
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM22:0 bit setting.
Table 14-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits
are set to a normal or CTC mode (non-PWM).
Table 14-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM
mode.
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-
Table 14-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase cor-
rect PWM mode.
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-
Bits 5:4 – COM2B1:0: Compare Match Output B Mode
These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0
bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin
must be set in order to enable the output driver.
Table 14-2.
Compare Output Mode, non-PWM Mode
COM2A1
COM2A0
Description
0
Normal port operation, OC0A disconnected.
0
1
Toggle OC2A on Compare Match
1
0
Clear OC2A on Compare Match
1
Set OC2A on Compare Match
Table 14-3.
Compare Output Mode, Fast PWM M
odeCOM2A1
COM2A0
Description
0
Normal port operation, OC2A disconnected.
01
WGM22 = 0: Normal Port Operation, OC0A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
10
Clear OC2A on Compare Match, set OC2A at BOTTOM,
(non-inverting mode).
11
Set OC2A on Compare Match, clear OC2A at BOTTOM,
(inverting mode).
Table 14-4.
Compare Output Mode, Phase Correct PWM Mode
COM2A1
COM2A0
Description
0
Normal port operation, OC2A disconnected.
01
WGM22 = 0: Normal Port Operation, OC2A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
10
Clear OC2A on Compare Match when up-counting. Set OC2A on
Compare Match when down-counting.
11
Set OC2A on Compare Match when up-counting. Clear OC2A on
Compare Match when down-counting.