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参数资料
| 型号： | MD82C237/B |
| 厂商： | INTERSIL CORP |
| 元件分类： | DMA控制器 |
| 英文描述： | 4 CHANNEL(S), 8 MHz, DMA CONTROLLER, CDIP40 |
| 封装： | SIDE BRAZED, DIP-40 |
| 文件页数： | 5/25页 |
| 文件大小： | 508K |
| 代理商： | MD82C237/B |
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registers to operate as in normal mode (Data-Width register
not accessible) until 16-bit transfer mode is again entered.
The four mask bits may also be cleared simultaneously by
using the Clear Mask Register command (see software com-
mands section). This command has no effect on the data-
width bits.
Temporary Register - The internal Temporary register is
used to hold data during memory-to-memory transfers. Fol-
lowing the completion of the transfers, the last byte moved
can be read by the microprocessor. In the case of 16-bit
transfers, only the least significant 8-bits of the last word
transferred are stored in this register. The Temporary regis-
ter always contains the last byte transferred in the previous
memory-to-memory operation, unless cleared by a RESET
or Master Clear.
Software Commands Affected by
16-Bit Mode
Master Clear - This software instruction has the same effect
as the hardware RESET. The Command, Status, Request,
and Temporary registers, and Internal First/Last Flip-Flop
and mode register counter are cleared and the Mask register
is set. When the Master Clear instruction occurs while in 16-
bit transfer mode, the 82C237 enters normal (8-bit) transfer
mode in the Idle cycle.
Clear Mask Register - This command clears the mask bits
of all four channels, enabling them to accept DMA requests.
This command has no effect on data-width bits in 16-bit
transfer mode.
OPERATION
A3A2A1A0
IOR
IOW
Read Status Register
1000
0
1
Write Command Register
1000
1
0
Read Request Register
1001
0
1
Write Request Register
1001
1
0
Read Command Register
1010
0
1
Write Single Mask Bit (Note 1)
1010
1
0
Write All Data-Width Bits (Notes 1, 2)
1010
1
0
Read Mode Register
1011
0
1
Write Mode Register
1011
1
0
Set First/Last F/F
1100
0
1
Clear First/Last F/F
1100
1
0
Read Temporary Register
1101
0
1
Master Clear
1101
1
0
Clear Mode Reg. Counter
1110
0
1
Clear Mask Register
1110
1
0
Read All Mask/Data-Width Bits (Note 2)
1111
0
1
Write All Mask Bits
1111
1
0
NOTES:
1. The register to be written is determined by data bit 3.
2. Data-Width bits exist in 82C237, 16-bit mode only.
FIGURE 5. 16-BIT MODE SOFTWARE COMMAND CODES AND REGISTER CODES
82C237
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