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参数资料
| 型号： | MD82C54-12/B |
| 厂商： | INTERSIL CORP |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 3 TIMER(S), PROGRAMMABLE TIMER, CDIP24 |
| 封装： | CERDIP-24 |
| 文件页数： | 13/19页 |
| 文件大小： | 380K |
| 代理商： | MD82C54-12/B |
3
Functional Description
General
The 82C54 is a programmable interval timer/counter
designed for use with microcomputer systems. It is a general
purpose, multi-timing element that can be treated as an
array of I/O ports in the system software.
The 82C54 solves one of the most common problems in any
microcomputer system, the generation of accurate time
delays under software control. Instead of setting up timing
loops in software, the programmer configures the 82C54 to
match his requirements and programs one of the counters
for the desired delay. After the desired delay, the 82C54 will
interrupt the CPU. Software overhead is minimal and vari-
able length delays can easily be accommodated.
Some of the other computer/timer functions common to micro-
computers which can be implemented with the 82C54 are:
Real time clock
Event counter
Digital one-shot
Programmable rate generator
Square wave generator
Binary rate multiplier
Complex waveform generator
Complex motor controller
Data Bus Buffer
This three-state, bi-directional, 8-bit buffer is used to inter-
face the 82C54 to the system bus (see Figure 1).
Read/Write Logic
The Read/Write Logic accepts inputs from the system bus and
generates control signals for the other functional blocks of the
82C54. A1 and A0 select one of the three counters or the Con-
trol Word Register to be read from/written into. A “low” on the
RD input tells the 82C54 that the CPU is reading one of the
counters. A “low” on the WR input tells the 82C54 that the CPU
is writing either a Control Word or an initial count. Both RD and
WR are qualified by CS; RD and WR are ignored unless the
82C54 has been selected by holding CS low.
CLK 2
18
I
CLOCK 2: Clock input of Counter 2.
A0, A1
19 - 20
I
ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write
operations. Normally connected to the system address bus.
CS
21
I
CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and
WR are ignored otherwise.
RD
22
I
READ: This input is low during CPU read operations.
WR
23
I
WRITE: This input is low during CPU write operations.
VCC
24
VCC: The +5V power supply pin. A 0.1F capacitor between pins VCC and GND is recommended
for decoupling.
Pin Description (Continued)
SYMBOL
DIP PIN
NUMBER
TYPE
DEFINITION
A1
A0
SELECTS
00
Counter 0
01
Counter 1
10
Counter 2
1
Control Word Register
CONTROL
WORD
REGISTER
COUNTER
2
COUNTER
1
COUNTER
0
INT
E
RNAL
BUS
OUT 2
GATE 2
CLK 2
OUT 1
GATE 1
CLK 1
OUT 0
GATE 0
CLK 0
WR
RD
D7 - D0
A0
A1
CS
FIGURE 1. DATA BUS BUFFER AND READ/WRITE LOGIC
FUNCTIONS
8
DATA/
BUS
BUFFER
READ/
WRITE
LOGIC
82C54
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MD82C54B | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MD82C54Q | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MD82C55/R | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MD82C55A | 制造商:HARRIS 制造商全称:HARRIS 功能描述:CMOS Programmable Peripheral Interface |
| MD82C55A/B | 制造商:Intersil Corporation 功能描述:CMOS PROGRAMMABLE PERIPHERAL INTRFC 40CDIP - Rail/Tube |
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