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参数资料
| 型号： | MH8S64DBKG-8 |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| 中文描述： | 536870912位（8388608 -文字，64位）SynchronousDRAM |
| 文件页数： | 25/55页 |
| 文件大小： | 588K |
| 代理商： | MH8S64DBKG-8 |
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MH8S64PHC -7,-8,-10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( 25
MITSUBISHI
ELECTRIC
9/ Dec. /1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0282-0.0
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of the same or the other bank.
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A10
DQ
Write
Yi
0
00
Write
Yk
0
10
Dai0
Daj0
Daj1
Dbk0
Write
Yj
0
00
Dbk1 Dbk2
Write
Yl
0
00
Dal0
Dal1
Dal2
Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank.
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The
input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CK
Command
A10
DQ
Write
Yi
0
00
Qaj0
READ
Yj
0
00
Qaj1
Dai0
Dbk0 Dbk1
DQMB0-7
Write
Yk
0
10
READ
Yl
0
00
Qbl0
A0-9
BA0,1
A0-9,11
BA0,1
A11
A11
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MH8S64DBKG-8L | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64FFC-10 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64FFC-10L | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64PHC-10 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64PHC-7 | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
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