参数资料
型号: MIC2164-3YMM
厂商: Micrel Inc
文件页数: 15/39页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 10-MSOP
产品培训模块: MIC2124 Synchronous Current Mode DC-DC Buck Controller
标准包装: 100
系列: Hyper Speed Control™
PWM 型: 混合物
输出数: 1
频率 - 最大: 1.25MHz
占空比: 66%
电源电压: 3 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 管件
产品目录页面: 1092 (CN2011-ZH PDF)
其它名称: 576-3544-5
I CL ≈
Micrel, Inc.
Figure 4. MIC2164/-2/-3 Current Limiting Circuit
Using the typical V CL value of 130mV, the current limit
value is roughly estimated as:
130mV
R DS(ON)
For designs where the current ripple is significant
compared to the load current I OUT , or for low duty cycle
operation, calculating the current limit I CL should take
into account that one is sensing the peak inductor
current and that there is a blanking delay of
approximately 150ns.
MIC2164/-2/-3/C
MOSFET Gate Drive
The MIC2164/-2/-3 high-side drive circuit is designed to
switch an N-Channel MOSFET. The block diagram of
Figure 1 shows a bootstrap circuit, consisting of D1 (a
Schottky diode is recommended) and C BST . This circuit
supplies energy to the high-side drive circuit. Capacitor
C BST is charged while the low-side MOSFET is on and
the voltage on the LX pin is approximately 0V. When the
high-side MOSFET driver is turned on, energy from C BST
is used to turn the MOSFET on. As the high-side
MOSFET turns on, the voltage on the LX pin increases
to approximately V HSD . Diode D1 is reversed biased and
C BST floats high while continuing to keep the high-side
MOSFET on. The bias current of the high-side driver is
less than 10mA so a 0.1 μ F to 1 μ F is sufficient to hold
the gate voltage with minimal droop for the power stroke
(high-side switching) cycle, i.e. Δ BST = 10mA x
3.33 μ s/0.1 μ F = 333mV for MIC2164. When the low-side
MOSFET is turned back on, C BST is recharged through
D1. A small resistor R G , which is in series with C BST , can
slow down the turn-on time of the high-side N-channel
MOSFET.
The drive voltage is derived from the supply voltage V IN .
The nominal low-side gate drive voltage is V IN and the
nominal high-side gate drive voltage is approximately V IN
– V DIODE , where V DIODE is the voltage drop across D1. An
approximate 30ns delay between the high-side and low-
I CL =
130mV
R DS(ON)
+
V OUT * T DLY
L
?
Δ I L(pp)
2
(2)
side driver transitions is used to prevent current from
simultaneously flowing unimpeded through both
MOSFETs.
Δ I L(pp) =
V OUT ? (1 ? D)
f SW ? L
(3)
where
V OUT = The output voltage
T DLY = Current limit blanking time, 150ns typical
Δ I L(pp) = Inductor current ripple peak-to-peak value
D = Duty Cycle
f SW = Switching frequency
The MOSFET R DS(ON)
varies 30 to 40% with
temperature; therefore, it is recommended to add a 50%
margin to I CL in the above equation to avoid false current
limiting due to increased MOSFET junction temperature
rise. It is also recommended to connect LX pin directly to
the drain of the low-side MOSFET to accurately sense
the MOSFETs R DS(ON) .
September 2010
15
M9999-091310-D
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