参数资料
| 型号： | MIC22602YML TR |
| 厂商： | Micrel Inc |
| 文件页数： | 10/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 24MLF |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.7V |
| 输入电压： | 2.6 V ~ 5.5 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘，24-MLF? |
| 包装： | 标准包装 |
| 供应商设备封装： | 24-MLF?（4x4） |
| 其它名称： | 576-3645-6 |
Micrel, Inc.
Functional Description
PVIN, SVIN
PVIN is the input supply to the internal 30m ? P-Channel
Power MOSFET. This should be connected externally to
the SVIN pin. The supply voltage range is from 2.6V to
5.5V. A 22μF ceramic is recommended for bypassing
each PVIN supply.
EN/DLY
This pin is internally fed with a 1μA current source from
VIN. A delayed turn on is implemented by adding a
capacitor to this pin. The delay is proportional to the
capacitor value. The internal circuits are held off until
EN/DLY reaches the enable threshold of 1.24V.
RC
RC allows the slew rate of the output voltage to be
programmed by the addition of a capacitor from RC to
ground. RC is internally fed with a 1μA current source
and VOUT slew rate is proportional to the capacitor and
the 1μA source. The RC pin cannot be left floating. Use
a minimum capacitor value of 470pF or larger.
DELAY
Adding a capacitor to this pin allows the delay of the
POR signal.
When VOUT reaches 90% of its nominal voltage, the
DELAY pin current source (1μA) starts to charge the
external capacitor. At 1.24V, POR is asserted high.
COMP
The MIC22602 uses an internal compensation network
containing a fixed frequency zero (phase lead response)
and pole (phase lag response) which allows the external
compensation network to be much simplified for stability.
The addition of a single capacitor and resistor will add
the necessary pole and zero for voltage mode loop
stability using low value, low ESR ceramic capacitors.
MIC22602
FB
The feedback pin provides the control path to control the
output. A resistor divider connecting the feedback to the
output is used to adjust the desired output voltage. Refer
to the feedback section in the “Applications Information”
for more detail.
POR
This is an open drain output. A 47.5k resistor can be
used for a pull up to this pin. POR is asserted high when
output voltage reaches 90% of nominal set voltage and
after the delay set by C DELAY . POR is asserted low
without delay when enable is set low or when the output
goes below the -10% threshold. For a Power Good (PG)
function, the delay can be set to a minimum. This can be
done by removing the DELAY capacitor.
SW
This is the connection to the drain of the internal P-
Channel MOSFET and drain of the N-Channel MOSFET.
This is a high frequency high power connection;
therefore traces should be kept as short and as wide as
practical.
SGND
Internal signal ground for all low power sections.
PGND
Internal ground connection to the source of the internal
N-Channel MOSFETs.
October 2009
10
M9999-102809-A
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