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参数资料
| 型号： | MIC2341R-2YTQ TR |
| 厂商： | Micrel Inc |
| 文件页数： | 6/32页 |
| 文件大小： | 1277K |
| 描述： | IC HOT PLUG CTLR DUAL PCI 48TQFP |
| 标准包装： | 2,000 |
| 类型： | 热交换控制器 |
| 应用： | 通用型，PCI Express? |
| 内部开关： | 无 |
| 电流限制： | 可调 |
| 电源电压： | 3.3V，12V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 带卷 (TR) |
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Micrel, Inc.
MIC2341/2341R
October 2007
6
M9999-102507-A
(408) 944-0800
Pin Description (cont.)
Pin Number
Pin Name
Pin Function
14
23
3VGATEA
3VGATEB
3V Gate Drive Outputs [A/B]: Each pin connects to the gate of an external N-
channel power MOSFET. During power-up, the C
GATE
(if used) and the C
GS
of
the external MOSFETs are connected to a 25礎 current source. This controls
the value of dv/dt seen at the source of the MOSFETs, and hence the current
flowing into the 3V load capacitance.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the FET for a period of t
FLT
or t
DFLT
(whichever is
shorter). Whenever an overcurrent, thermal shutdown, or input undervoltage
fault condition occurs, the corresponding 3VGATE pin for the affected slot is
pulled down to AGND to turn OFF the external MOSFET.
11
26
VSTBYA
VSTBYB
3.3V Standby Supply Voltage: Required to support the PCI Express VAUX
output. Additionally, all internal logic circuitry operates on VSTBY[A/B]. An
internal UVLO circuit prevents turn-on of the external 3.3VAUX supply until the
voltage at the VSTBY[A/B] pins is higher than the V
UVLO(STBY)
threshold voltage.
Both pins must be externally connected together at the MIC2341 controller.
15
22
VAUXA
VAUXB
3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect the
3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal 0.4-&
MOSFETs. These outputs are current limited and protected against short-circuit
faults.
44
43
ONA
ONB
Main +12VOUT[A/B] and +3.3VOUT[A/B] Enable Inputs: These level-sensitive
digital inputs are each internally connected with pull-up resistors to VSTBY[A]
and are used to enable or disable the MAIN[A/B] (+3.3V and +12V) outputs.
Applying a high-to-low transition on ON[A/B] for at least 200ns (t
LPW
) after a fault
resets the +12V and/or +3.3V fault latches for the affected slot and de-asserts
the /FAULT_MAIN[A/B] output signals. The +12V and/or the +3.3V electronic
circuit breakers are reset once the /FAULT_MAIN[A/B] output signals are de-
asserted.
45
42
AUXENA
AUXENB
VAUX[A/B] Enable Inputs: These level-sensitive digital inputs are each internally
connected with pull-up resistors to VSTBY[A] and are used to enable or disable
the VAUX[A/B] outputs. Applying a high-to-low transition on AUXEN[A/B] for at
least 200ns (t
LPW
) after a fault resets the VAUX fault latches for the affected slot
and de-asserts the /FAULT_AUX[A/B] output signals. The VAUX[A/B] electronic
circuit breakers are reset once the /FAULT_AUX[A/B] output signals are de-
asserted.
2
35
CFILTERA
CFILTERB
Overcurrent Filter Capacitor [A/B]: Capacitors connected between these pins
and AGND set the duration of t
FLT
, the response time of the primary overcurrent
(OC) detector circuits. t
FLT
is the amount of time for which a slot remains in
current limit before its circuit breaker is tripped. To configure the controller to use
its internal digital filter delay timer, CFILTER[A/B] pins shall be connected to
AGND
6
31
/PWRGDA
/PWRGDB
/PWRGD[A/B] are open-drain, asserted active-LOW digital outputs that are
normally connected by an external 10k& pull-up resistor (each) to VSTBY. Each
output signal is asserted when inputs signals ON[A/B] and AUXEN[A/B] have
been enabled, each output voltage has crossed its respective Power-is-Good
output threshold (V
UVTH(12V)
, V
UVTH(3V)
, and V
UVTH(VAUX)
threshold voltages), and no
fault conditions exist . Please consult the /PWRGD[A/B] and the
/DLY_PWRGD[A/B] state diagrams in the Applications Information section for
more detail.
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