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参数资料
| 型号： | MIC2341R-2YTQ TR |
| 厂商： | Micrel Inc |
| 文件页数： | 7/32页 |
| 文件大小： | 1277K |
| 描述： | IC HOT PLUG CTLR DUAL PCI 48TQFP |
| 标准包装： | 2,000 |
| 类型： | 热交换控制器 |
| 应用： | 通用型，PCI Express? |
| 内部开关： | 无 |
| 电流限制： | 可调 |
| 电源电压： | 3.3V，12V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 带卷 (TR) |
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Micrel, Inc.
MIC2341/2341R
October 2007
7
M9999-102507-A
(408) 944-0800
Pin Description (cont.)
Pin Number
Pin Name
Pin Function
1
36
/FAULT_MAINA
/FAULT_MAINB
/FAULT_MAIN[A/B] Outputs are open-drain, asserted active-LOW digital outputs
that are normally connected by an external 10k& resistor to VSTBY. Asserted
whenever the primary or secondary circuit breaker trips because of an overcurrent
fault condition or an input undervoltage. Applying a high-to-low transition at the
ON[A/B] pin resets the /FAULT_MAIN[A/B] outputs if /FAULT_MAIN[A/B] was
asserted in response to a fault condition on one of the slots MAIN outputs (+12V or
+3.3V). If an overcurrent event asserted /FAULT_MAIN[A/B], the respective outputs
circuit breaker is reset when
/FAULT_MAIN[A/B] output signal is de-asserted. A 200ns minimum pulse width
(t
LPW
) for ON[A/B] will reset the MAIN outputs in the event of an overcurrent fault
once the fault is removed.
If a fault condition occurred on both the MAIN and VAUX outputs of the same slot,
then a high-to-low transition on both ON[A/B] and AUXEN[A/B] must be applied to
de-assert the /FAULT_MAIN[A/B] and /FAULT_AUX[A/B] outputs.
To simplify system fault reporting, the /FAULT_MAIN[A/B] output pins may be
connected together with the /FAULT_AUX[A/B] output pins.
4
39
/CRSWA
/CRSWB
Card Retention Switch Inputs [A/B]. These are level sensitive, asserted active- LOW
digital inputs with internal pull-up resistors to VSTBY[A]. These inputs can be
connected to the PRNST#1 or PRNST#2 pins on a PCIe connector to indicate to the
MIC2341 that a PCIe plug-in card is present and firmly mated. Internally, the
MIC2341s +12VGATE[A/B], +3VGATE[A/B], and 3VAUX[A/B] gate drive circuits are
gated with the MIC2341s ON[A/B] and the AUXEN[A/B] inputs to deliver power to
the connector only when a PCIe plug-in card is present. During operation, if the
/CRSW[A/B] inputs are disconnected or if there is a pc board trace failure, all
outputs on the respective slot are turned OFF without delay. Each of these inputs
exhibit an internal switch debounce delay of approximately 10ms.
48
37
/FAULT_AUXA
/FAULT_AUXB
/FAULT_AUX[A/B] Outputs are open-drain, asserted active-LOW digital outputs that
are normally connected by an external 10k& resistor to VSTBY. Asserted whenever
the VAUX[A/B] circuit breaker trips because of an overcurrent fault condition or a
slot/die overtemperature condition. Applying a high-to-low transition at the
AUXEN[A/B] pin for at least 0.5祍 resets the /FAULT_AUX[A/B] outputs if the
/FAULT_AUX[A/B] output signal was asserted in response to a fault condition on the
respective slots VAUX output. If an overcurrent event asserted /FAULT_AUX[A/B],
the respective outputs VAUX circuit breaker is reset when /FAULT_AUX[A/B] output
signal is de-asserted. A 200ns minimum pulse width (t
LPW
) for AUX_EN[A/B] will
reset the MAIN outputs in the event of an overcurrent fault once the fault is
removed.
If a fault condition occurred on both the MAIN and VAUX outputs of the same slot,
then a high-to-low transition on both ON[A/B] and AUXEN[A/B] must be applied to
de-assert the /FAULT_MAIN[A/B] and /FAULT_AUX[A/B] outputs.
To simplify system fault reporting, the /FAULT_AUX[A/B] output pins may be
connected together with the /FAULT_MAIN[A/B] output pins.
9
28
/FORCE_ONA
/FORCE_ONB
Force On Enable Inputs [A/B]: These active-LOW, level-sensitive inputs with internal
pull-up current (礎) to VSTBY[A] will turn on all three of the respective slots outputs
(+12V, +3.3V, and VAUX), while specifically defeating all protections on those
supplies when asserted. This explicitly includes all overcurrent and short circuit
protections and on-chip thermal protection for the VAUX[A/B] supplies. Additionally
included are the UVLO protections for the +3.3V and +12V main supplies. The
/FORCE_ON[A/B] pins do not
disable UVLO protection for the VAUX[A/B] supplies.
These input pins are intended for diagnostic purposes only.
Asserting /FORCE_ON[A/B] will cause the respective slots /PWRGD[A/B] and
/DLY_PWRGD[A/B] output signals to be asserted LOW and cause the
/FAULT_MAIN[A/B], the /FAULT_AUX[A/B], the /INT, and the SYSPWRGD output
signals to their open-drain state.
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