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参数资料
| 型号： | MIC3000BMLTR |
| 厂商： | MICREL INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC24 |
| 封装： | 4 X 4 MM, MLF-24 |
| 文件页数： | 2/68页 |
| 文件大小： | 444K |
| 代理商： | MIC3000BMLTR |
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MIC3000
Micrel
M9999-101204
10
October 2004
Electrical Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
Control and Status I/O Timing, TXFAULT, TXDISABLE, RSIN, RSOUT, and RXLOS
tOFF
TXDISABLE Assert Time
From input asserted to optical output at
10
s
10% of nominal, CCOMP = 10nF.
tON
TXDISABLE De-assert Time
From input de-asserted to optical output
1
ms
at 90% of nominal, CCOMP = 10nF.
tINIT
Initialization Time
From power on or transmitter enabled to
300
ms
optical output at 90% of nominal and
TX_FAULT de-asserted.(4)
tINIT2
Power-on Initialization Time
From power on to APC loop enabled.
200
ms
tFAULT
TXFAULT Assert Time
From fault condition to TXFAULT
95
s
assertion.(4)
tRESET
Fault Reset Time
Length of time TXDISABLE must be
10
s
asserted to reset fault condition.
tLOSS_ON
RXLOS Assert Time
From loss of signal to RXLOS asserted.
95
s
tLOSS_OFF
RXLOS De-assert Time
From signal acquisition to LOS
100
s
de-asserted.
tDATA
Analog Parameter Data Ready
From power on to valid analog parameter
400
ms
data available.(4)
tPROP_IN
TXFAULT, TXDISABLE, RXLOS,
Time from input change to corresponding
1
s
RSIN Input Propagation Time
internal register bit set or cleared.(4)
tPROP_OUT
TXFAULT, RSOUT, /INT Output
From an internal register bit set or cleared
1
s
Propagation Time
to corresponding output change.(4)
Fault Comparators
φ
FLTTMR
Fault Suppression Timer Clock
Note 4
0.475
0.5
0.525
ms
Period
Accuracy
-3
+3
%F.S.
tREJECT
Glitch Rejection
Maximum length pulse that will not cause
4.5
s
output to change state.(4)
VSAT
Saturation Detection Threshold
High level
95
%VDDA
Low level
5
%VDDA
Power-On Hour Meter
Timebase Accuracy
0°C - TA - +70°C(4)
+5
–5
%
–40°C - TA - +105°C
+10
–10
%
Resolution
Note 4
10
hours
Non-Volatile (FLASH) Memory
tWR
Write Cycle Time(8)
From STOP of a one to four-byte write
13
ms
transaction.(4)
Data Retention
100
years
Endurance
Minimum Permitted Number Write
10,000
cycles
Cycles
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