参数资料
型号: MIC5164YMM
厂商: Micrel Inc
文件页数: 11/23页
文件大小: 0K
描述: IC REG CTLR DUAL DDR2/3 10MSOP
特色产品: MIC5164 Dual Regulator
标准包装: 100
应用: 控制器,DDR3,GDDR3/4/5
输入电压: 1.35 V ~ 6 V
输出数: 1
输出电压: 可编程
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 管件
其它名称: 576-3721-5
Micrel, Inc.
Power dissipation in an SSTL circuit will be identical for
both the high-side and low-side MOSFETs. Since the
supply voltage is divided by half to supply V TT , both
MOSFETs have the same voltage dropped across them.
They are also required to be able to sink and source the
same amount of current (for either all 0’s or all 1’s). This
equates to each side being able to dissipate the same
amount of power. Power dissipation calculation for the
MIC5164
In our example of a 3A peak SSTL_2 termination circuit,
we have selected a D-pack N-Channel MOSFET that
has a maximum junction temperature of 125°C. The
device has a junction-to-case thermal resistance of
1.5°C/Watt. Our application has a maximum ambient
temperature of 60°C. The required junction-to-ambient
thermal resistance can be calculated as follows:
high-side driver is as follows:
P D = (V DDQ ? V TT ) × I_SOURCE
θ JA =
T J ? T A
P D
where I_SOURCE is the average source current. Power
dissipation for the low-side MOSFET is as follows:
Where T J is the maximum junction temperature, T A is the
maximum ambient temperature and P D is the power
dissipation.
In our example:
P D = V TT × I_SINK
where I_SINK is the average sink current.
In a typical 3A peak SSTL_2 circuit, power
considerations for MOSFET selection would occur as
follows:
θ JA =
θ JA =
T J ? T A
P D
125 ° C - 60 ° C
2 W
θ JA = 32 . 5 ° C / W
P D = (V DDQ ? V TT ) × I_SOURCE
P D = (2.5V ? 1.25V) × 1.6A
P D = 2W
This typical SSTL_2 application would require the high-
side and low-side N-Channel MOSFETs to be able to
handle 2 Watts each. In higher current applications,
multiple N-Channel MOSFETs may be placed in parallel
to spread the power dissipation. These MOSFETs will
share current, distributing power dissipation across each
device.
The maximum MOSFET die (junction) temperature limits
maximum power dissipation. The ability of the device to
dissipate heat away from the junction is specified by the
junction-to-ambient ( θ JA ) thermal resistance.
This is the sum of junction-to-case ( θ JC ) thermal
resistance, case-to-sink ( θ CS ) thermal resistance and
sink-to-ambient ( θ SA ) thermal resistance:
θ JA = θ JC + θ CS + θ SA
This shows that our total thermal resistance must be
better than 32.5°C/W. Since the total thermal resistance
is a combination of all the individual thermal resistances,
the amount of heat sink required can be calculated as
follows:
θ SA = θ JA ? ( θ JC + θ CS )
In our example:
θ SA = 32 . 5 ° C / W - ( 1 . 5 ° C / W + 0 . 5 ° C / W )
θ SA = 30 . 5 ° C / W
In most cases, case-to-sink thermal resistance can be
assumed to be about 0.5°C/W.
The SSTL termination circuit for our example, using two
D-pack N-Channel MOSFETs (one high-side and one
low-side) will require enough copper area to spread the
heat from the MOSFET. In this example to dissipate 2W
from TO-252 package a 2 oz copper of 1.0 in 2 on
component side is required. In some cases, airflow may
also help to reduce thermal resistance. For different
MOSFET package refer to manufacturer Data Sheet for
copper area requirements.
June 2010
11
M9999-061510
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