参数资料
型号: MIC5164YMM
厂商: Micrel Inc
文件页数: 9/23页
文件大小: 0K
描述: IC REG CTLR DUAL DDR2/3 10MSOP
特色产品: MIC5164 Dual Regulator
标准包装: 100
应用: 控制器,DDR3,GDDR3/4/5
输入电压: 1.35 V ~ 6 V
输出数: 1
输出电压: 可编程
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 管件
其它名称: 576-3721-5
Micrel, Inc.
Application Information
High-performance memory requires high-speed
signaling. This requires special attention to maintain
signal integrity. Bus termination provides a means to
increase signaling speed while maintaining good signal
integrity. An example of bus termination is the Series
Stub Termination Logic or SSTL. Figure 2 is an example
of an SSTL 2 single-ended series parallel terminated
output. SSTL 2 is a JEDEC signaling standard operating
off a 2.5V supply. It consists of a series resistor (R S ) and
a terminating resistor (R T ). Values of R S range between
10 ? to 30 ? with a typical of 22 ? , while R T ranges from
22 ? to 28 ? with a typical value of 25 ? . V REF must
maintain 1/2 VDD with a ±1% tolerance, while V TT will
dynamically sink and source current to maintain a
termination voltage of ±40mV from the V REF line under all
conditions. This method of bus termination reduces
common mode noise, settling time, voltage swings,
EMI/RFI and improves slew rates.
The MIC5165 provides two drive signals, the high-side
MOSFET acts as a pass element to provide output
voltage and low side MOSFET acts as pull-down to
regulate the output termination voltage (V TT ). An internal
error amplifier compares the termination voltage (V TT )
and V REF , controlling two external N-Channel MOSFETs
to sink and source current to maintain a termination
voltage (V TT ) equal to V REF . The N-Channels receive
their enhancement voltage from a separate VCC pin on
the device.
Although the general discussion is focused on SSTL, the
MIC5164 is also capable of providing bus terminations
for SCSI, GTL, HSTL, LV-TTL, Rambus, LV-PECL,
DDR, DDR2, DDR3 memory termination and other
systems.
MIC5164
VDDQ
The VDDQ pin on the MIC5164 provides the source
current through the high-side N-Channel and the
reference voltage to the device. The MIC5164 can
operate at V DDQ voltages as low as 1.35V. Due to the
possibility of large transient currents being sourced from
this line, significant bypass capacitance will aid in
performance by improving the source impedance at
higher frequencies. Since the reference is simply V DDQ /2,
perturbations on V DDQ will also appear at half the
amplitude on the reference. For this reason, low-ESR
capacitors such as ceramics or OS-CON are
recommended on V DDQ .
V TT
V TT is the actual termination point. V TT is regulated to
V REF . Due to high speed signaling, the load current seen
by V TT is constantly changing. To maintain adequate
large signal transient response, large OS-CON and
ceramics are recommended on V TT . The proper
combination and placement of the OS-CON and ceramic
capacitors is important to reduce both ESR and ESL
such that high-current and high-speed transients do not
exceed the dynamic voltage tolerance requirement of
V TT . The larger OS-CON capacitors provide bulk charge
storage while the smaller ceramic capacitors provide
current during the fast edges of the bus transition. Using
several smaller ceramic capacitors distributed near the
termination resistors is typically important to reduce the
effects of PCB trace inductance.
VREF
A minimum capacitor value of 120pF from VREF to
ground is required to remove high-frequency signals
reflected from the source (Refer to Figure 4). Large
capacitance values (>1500pF) should be avoided.
Values greater than 1500pF slow down V REF and detract
from the reference voltage’s ability to track V DDQ during
high-speed load transients.
Figure 2. SSTL-2 Termination
Figure 3. MIC5164 as a DDR Memory Termination
for 3.5A Application
June 2010
9
M9999-061510
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