MK1449B
Sound/SCSI+Fast Ethernet Clock
MDS 1449B C
3
Revision 120799
Printed 11/15/00
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126 (408)295-9800tel www.icst.com
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
-0.5
VDD+0.5
V
Clock Output
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Industrial temperature
-40
85
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Operating Voltage, VDD
3
5.5
V
Input High Voltage, VIH, ICLK only
ICLK (Pin 1)
(VDD/2)+1
VDD/2
V
Input Low Voltage, VIL, ICLK only
ICLK (Pin 1)
VDD/2
(VDD/2)-1
V
Input High Voltage, VIH
S0, S1
VDD-0.5
V
Input Low Voltage, VIL
S0, S1
0.5
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
IDD Operating Supply Current, 5V
No Load, 25, 40MHz
18
mA
IDD Operating Supply Current, 3.3V
No Load, 25, 40MHz
10
mA
Short Circuit Current
CLK output
±70
mA
On-Chip Pull-up Resistor
Pin 7
270
k
Input Capacitance, S1, S0
Pins 6, 7
4
pF
AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Input Frequency, crystal input
10
14.31818
27
MHz
Input Frequency, clock input
10
14.31818
50
MHz
Output Frequency
VDD = 3.0 to 5.5V
10
75
MHz
Output Clock Rise Time
0.8 to 2.0V
1
ns
Output Clock Fall Time
2.0 to 0.8V
1
ns
Output Clock Duty Cycle
at VDD/2
40
49 to 51
60
%
Synthesis error, 25, 40 MHz
1
ppm
Synthesis error, 12.288, 49.152 MHz
1
ppm
Absolute Clock Period Jitter, 20 pF load
Deviation from mean
±240
ps
One Sigma Clock Period Jitter, 20 pF load
100
ps
Electrical Specifications