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参数资料
| 型号： | MK1492-02RTRLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | 0.150 INCH, SSOP-28 |
| 文件页数： | 2/7页 |
| 文件大小： | 70K |
| 代理商： | MK1492-02RTRLF |
MK1492-02
Intel Mobile/SDRAM Clock Source
MDS1492-02E
2
Revision 2028
Printed 2/2/98
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY INFORMATION
ICRO
CLOCK
Pin #
Name
Type Description
1, 20, 26
VDD
P
Connect to +3.3V. Must be same voltage on all pins.
2
XI
I
Crystal connection. Connect to a 14.31818 MHz crystal or input clock.
3
XO
O
Crystal connection. Connect to a 14.31818 MHz crystal, or leave unconnected for clock.
4, 11, 17, 23
GND
P
Connect to Ground.
5
14.3(OE)
O/TI 14.318 MHz output. Amplitude matches VDD. Tri-State input control for all clocks.
6
SDCLK
I
I C Serial Port Clock
7
SDATA
I
I C Serial Port Data
8, 10
HOST 1,2
O
Host Output Clocks 1, 2. Amplitude matches VDD
. Auto adjusts for low skew at 2.5 V.
9, 14
VDD
P
Connect to CPU VDD supply (3.3V or 2.5V).
12, 13, 18
HOST 3,4,5,7
O
Host Output Clocks. HOST7,8 enabled by DS input per table above.
15
CPUS#
TI
CPU Stop power down control; defined in table above. Signal connection on page 7.
16
PCISTP#
TI
PCI Stop power down control; defined in table above. Signal connection on page 7.
19
HOST6,8(DS)
I/O
Host Output Clock and DS input. HOST7,8 enabled by DS input per table above.
21
48M/24M(SEL0)
I/O
Fixed frequency clock and fixed frequency select input per table above.
22
PCIF(LE)
I/O
PCI Output clock that continues to run in PCI STOP mode. Low EMI enable input.
24
PCI(FS)
I/O
PCI Output clock, and CPU Frequency Select input. See PCIF and PCI tables above.
25
PCI(SEL1)
O/TI PCI Output clock, andSEL1 Select input. See PCIF and F1 tables above.
27
PCI(CSSS)
I/O
PCI output clock and CPU slow or stop mode select input per table above.
28
F1(PEN)
O/TI F1 clock output and PCIF Enable input.
Pin Descriptions
Host/PCI Frequency Select Table
Pin Assignment
1
8
9
2
3
4
5
6
7
10
11
12
13
14
16
15
20
17
18
19
25
24
23
22
21
26
27
28
VDDHOST1,2
SDATA
SDCLK
XO
VDD
14.3(OE)
HOST2
HOST1
XI
GND
VDDHOST3,4
GND
HOST4
HOST3
HOST1,2 or 3,4
48M/24M Frequency
Select Table (MHz)
Power Down Control Table
PCISTP# CPUS# CSSS
MODE
HOST3:8
HOST1,2 PCI
PCIF 48/24 14.3 DESCRIPTION
1
X
ON
ON All Clocks On.
0
1 or M
X
PCI STOP
U
LOW
U
PCI Outputs synchronously enter and leave low state .
X
M
0
CPU SLOW
33MHz
33 MHz
U
16.6M ON
ON Host smooth transition to/from 33 MHz.
X
M
1
CPU STOP
ON
LOW
U
ON
ON Host Outputs synchronously enter and leave low state.
X
0
X
Power Down
LOW
LOW LOW LOW LOW All outputs low. PLLs and Oscillator off.
M
X
PLL STOP
LOW
LOW LOW LOW
ON Oscillator on. PLLs off.
OE
ALL CLOCK OUTPUTS
0
TRISTATED
M, 1
ENABLED
Output Enable Control Table
SEL0
48M/24M
0
24.0
1
48.0
EMI Control
LE
Low EMI
0
ON
1
OFF
HOST1,2
Key: I = Input, TI = tri-level input, O = Output, P = Power supply connection, I/O = Input on power up, becomes an Output after 10ms
SEL1
F1
0
PCI
M
14.318
1
24.0
F1 Frequency Select
VDD
PCIF(LE)
GND
VDD
F1(PEN)
HOST6,8(DS)
48M/24M(SEL0)
PCI(CSSS)
PCI(SEL1)
CPUS#
HOST5,7
PCISTP#
GND
PCI(FS)
PEN
Pin 25
Pin 24
0
PCI
M
PCI
PCIF
1
PCIF
PCIF Enable Control
Key: 1 = connected to VDD, 0 = connected to ground, M = VDD/2, X = any valid logic level, U = unchanged (not affected) from previous state.
Combination Input/Outputs should be connected to VDD or Ground through a 10 k
resistor as shown on page 7.
OE=M
OE=1
CPUS#
CSSS
FS
HOST
1
X
0
60.0
50.0
1
X
1
66.66
75.0
M
0
X
33.33
DS
HOST7,8
0
ENABLED
1
TRISTATED
HOST7,8 Enable
2
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