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参数资料
| 型号： | MK1573-03S |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 60.41957 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封装： | 0.150 INCH, SOIC-16 |
| 文件页数： | 2/5页 |
| 文件大小： | 68K |
| 代理商： | MK1573-03S |
MK1573-03
GenClock HSYNC to Video Clock
MDS1573-03 A
2
111301
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800 www.icst.com
Number
Name
Type Description
1
HSYNC
I
HSYNC clock input. The output clocks are synchronized to the HSYNC falling edge.
2
VDD
P
Connect to +3.3V.
3
VDD
P
Connect to +3.3V.
4
CAP1
I
Connect a 0.047F ceramic NP0 capacitor and a 22k
resistor in series and also a parallel .0022F low leakage capacitor between this pin and CAP2.
5
GND
P
Connect to ground.
6
CAP2
I
Connect a 0.047F ceramic NP0 capacitor and a 22k
resistor in series and also a parallel .0022F low leakage capacitor between this pin and CAP1.
7
GND
P
Connect to ground.
8
FS0
I
Frequency Select 0. Determines CLK outputs (with given input) per table above.
9
CLK3
O
Clock 3 determined by status of FS3:0 per table above.
10
CLK1
O
Clock 1 determined by status of FS3:0 per table above.
11
OE
I
Output Enable. Tri-states the three output clocks when low.
12
CLK2
O
Clock 2 determined by status of FS3:0 per table above.
13
FS1
I
Frequency Select 1. Determines CLK outputs (with given input) per table above.
14
FS2
I
Frequency Select 2. Determines CLK outputs (with given input) per table above.
15
N/C
-
No connect. Nothing is connected to this pin.
16
FS3
I
Frequency Select 3. Determines CLK outputs (with given input) per table above.
Pin Descriptions
Type: I = Input, O = output, P = power supply connection
Pin Assignment
Output Clocks Decoding Table MK1573-03 (MHz)
16 pin (150 mil) SOIC
1
16
2
3
4
15
14
13
CAP1
GND
VDD
FS1
OE
5
6
7
8
12
11
10
9
FS0
FS2
CAP2
FS3
CLK2
CLK3
GND
CLK1
VDD
HSYNC
N/C
0 = connect directly to ground, 1 = connect directly to VDD.
CLK2 is a recovered HSYNC (with 50% duty cycle) on selections in italic.
HSYNC reference outputs on CLK3 (in italic) are inverted, recovered HSYNC.
Decode Address
HSYNC
Multiplier
CLK 1
CLK 2
CLK 3
FS3:0
(Hex)
pin 1
On-chip
pin 10
pin 12
pin 9
0
15.625k
2270
35.46875M
15.62k
31.25k
1
15.734264k
1820
28.63636M 15.734264k
31.4685k
2
15.625k
1728
27M
13.5M
15.625k
3
15.734264k
1716
27M
13.5M
15.734264k
4
15.625k
960
15M
7.5M
15.625k
5
15.734264k
953 1/3
15M
7.5M
15.734264k
6
15.625k
3840
60M
30M
15.625k
7
15.734264k
3840
60.41957M 30.20979M 15.734264k
8
15.625k
2270
35.46875M 17.734375M 4.433594M
9
15.734264k
1820
28.63636M 14.31818M
3.579545M
A
15.625k
2270
35.46875M
15.625k
B
15.734264k
1820
28.63636M 15.734264k 15.734264k
C
15.625k
2048
32M
16M
15.625k
D
15.734264k
808
12.71329M 15.734264k
31.4685k
E
15.734264k
1218
19.164M
Off
F
15.625k
1260
19.6875M
Off
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
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相关代理商/技术参数 |
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| MK1574 | 制造商:ICS 制造商全称:ICS 功能描述:Frame Rate Communications PLL |
| MK1574-01AS | 功能描述:IC PLL FRAME RATE COMM 16-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| MK1574-01ASI | 功能描述:时钟发生器及支持产品 FRAME RATE COMMUNICATION PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK1574-01ASITR | 功能描述:IC PLL FRAME RATE COMM 16-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| MK1574-01ASTR | 功能描述:时钟发生器及支持产品 FRAME RATE COMMUNICATION PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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