- 您现在的位置：买卖IC网 > PDF目录26830 > MK1575-01GITR (INTEGRATED DEVICE TECHNOLOGY INC) 1575 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 PDF资料下载
参数资料
| 型号： | MK1575-01GITR |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 1575 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16 |
| 文件页数： | 10/14页 |
| 文件大小： | 276K |
| 代理商： | MK1575-01GITR |
MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
IDT CLOCK RECOVERY PLL
5
MK1575-01
REV P 051310
Setting PLL Loop Bandwidth and
Damping Factor
The frequency response of the MK1575-01 PLL may be
approximated by the following equation:
Normalized PLL Bandwidth
The associated damping factor is calculated as follows:
Damping factor,
Where:
KO =
VCO gain in Hz/Volt
(use 340 MHz/V)
Icp =
Charge pump current, 12.5
A
N
=
Total feedback divide from VCO,
(Refer to N Value table, below)
CS =
External loop filter capacitor in Farads
RS =
Loop filter resistor in Ohms
The above bandwidth equation calculates the “normalized”
loop bandwidth which is approximately equal to the - 3dB
bandwidth. This approximate calculation does not take into
account the effects of damping factor or the third pole
imposed by CP. It does, however, provide a useful
approximation of filter performance.
To prevent jitter on the output clocks due to modulation of
the PLL by the input reference frequency, the following
general rule should be observed:
In general, the loop damping factor should be 0.7 or greater
to ensure output stability. For video applications, a low
damping factor (0.7 to 1.0) is generally desired for fast
genlocking. For telecom applications, a higher damping
factor is usually desirable. A higher damping factor will
create less passband gain peaking which will minimize the
gain of network clock wander amplitude. A higher damping
factor may also increase output clock jitter when there is
excess digital noise in the system application, due to the
reduced ability of the PLL to respond to, and therefore
compensate for, phase noise ingress.
Notes on setting the value of CP
As another general rule, the following relationship should be
maintained between components C1 and C2 in the external
loop filter:
Where:
CB = External bypass capacitor in Farads
Note that the MK1575-01 contains an internal 300 pF filter
cap which is connected in parallel with external device CB.
This helps to reduce output clock jitter. In some applications
external device CB will not be required.
CP establishes a second pole in the PLL loop filter. For
higher damping factors (>1), calculate the value of CP based
on a CS value that would be used for a damping factor of 1.
This will minimize baseband peaking and loop instability that
can lead to output jitter.
CP also helps to damp VCO input voltage modulation
caused by the charge pump correction pulses. A CP value
that is too low will result in increased output phase noise at
the phase detector frequency due to this. In extreme cases
where input jitter is high, charge pump current is high, and
CP is too small, the VCO input voltage can hit the supply or
ground rail resulting in non-linear loop response.
The best way to set the value of CP is to use the External
Loop Filter Solver located on the IDT web site.
R
S
K
O
I
CP
()
2
π N
-----------------------------------------------
=
ζ
R
S
2
--------
K
O
I
CP
C
S
N
------------------------------------------
=
PLL Bandwidth
f
Phase Detector
20
--------------------------------
≤
C
P
C
S
20
------
=
C
P
C
B
300 pF
+
=
相关PDF资料 |
PDF描述 |
|---|---|
| MK1707SLFTR | 1707 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| MK1707STR | PLL BASED CLOCK DRIVER, PDSO8 |
| MK1707STR | PLL BASED CLOCK DRIVER, PDSO8 |
| MK1707S | PLL BASED CLOCK DRIVER, PDSO8 |
| MK1709AGLF | 1709 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MK1575-01GLF | 功能描述:时钟发生器及支持产品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK1575-01GLFTR | 功能描述:时钟发生器及支持产品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK1575-01GTR | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| MK1581-01 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:LOW PHASE NOISE T1/E1 CLOCK GENERATOR |
| MK1581-01GI | 功能描述:IC CLK GENERATOR T1/E1 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
发布紧急采购，3分钟左右您将得到回复。