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参数资料
| 型号： | MK1575-01GITR |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 1575 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16 |
| 文件页数： | 13/14页 |
| 文件大小： | 276K |
| 代理商： | MK1575-01GITR |
MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
IDT CLOCK RECOVERY PLL
8
MK1575-01
REV P 051310
This above set of requirements is served by the circuit
illustrated in the Optimum Power Supply Connection, below.
The main features of this circuit are as follows:
Only one connection is made to the PCB power plane.
The capacitors and ferrite chip (or ferrite bead) on the
common device supply form a lowpass ‘pi’ filter that
remove noise from the power supply as well as clock
noise back toward the supply. The bulk capacitor should
be a tantalum type, 1
F minimum. The other capacitors
should be ceramic type.
The power supply traces to the individual VDD pins
should fan out at the common supply filter to reduce
interaction between the device circuit blocks.
The decoupling capacitors at the VDD pins should be
ceramic type and should be as close to the VDD pin as
possible. There should be no vias between the
decoupling capacitor and the supply pin.
Optimum Power Supply Connection
Series Termination Resistor
Output clock PCB traces over 1 inch should use series
termination to maintain clock signal integrity and to reduce
EMI. To series terminate a 50
trace, which is a commonly
used PCB trace impedance, place a 33
resistor in series
with the clock line as close to the clock output pin as
possible. The nominal impedance of the clock output is 20
.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following printed circuit board layout
recommendations should be observed.
1) Each 0.01F power supply decoupling capacitor should
be mounted as close to the VDD pin as possible. The PCB
trace to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via. Distance of the
ferrite chip and bulk decoupling from the device is less
critical.
2) The loop filter components (RZ, CS and CB) must also be
placed close to the CHGP and VIN pins. CB should be
closest to the device. Coupling of noise from other system
signal traces should be minimized by keeping traces short
and away from active signal traces. Use of vias should be
avoided.
3) To minimize EMI the 33
series termination resistor, if
needed, should be placed close to the clock output.
4) Because each input selection pin includes an internal
pull-up device, those inputs requiring a logic high state (“1”)
can be left unconnected. The pins requiring a logic low state
(“0”) can be grounded.
Loss of Reference Clock
If a loss occurs on the REFIN clock, the output frequency
will decrease at a rate of
where:
C = C1 + C2
VS = value of VS divider (from the table on page 3)
If the input is held low, the output will stop high or low, or
might toggle at several Hz.
Low Frequency Operation
The output frequency can be extended below 1.5 MHz by
adding a divider in the output path. In this configuration, it is
desirable to take the feedback signal from CLK1 rather than
the output of the divider. However, if zero delay operation is
required, the feedback signal must come from the divider
output.
Connection Via to 3.3V
Power Plane
Ferrite
Chip
0.
1
F
BULK
1nF
VDDA
Pin
0.
01
F
VDDD
Pin
0.
01
F
10
df
dt
4250
C x VS
=
Hz/s
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK1575-01GLF | 功能描述:时钟发生器及支持产品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK1575-01GLFTR | 功能描述:时钟发生器及支持产品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK1575-01GTR | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| MK1581-01 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:LOW PHASE NOISE T1/E1 CLOCK GENERATOR |
| MK1581-01GI | 功能描述:IC CLK GENERATOR T1/E1 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
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