参数资料
型号: MK1581-01GILFTR
厂商: IDT, Integrated Device Technology Inc
文件页数: 11/11页
文件大小: 0K
描述: IC CLK GENERATOR T1/E1 16-TSSOP
标准包装: 2,500
类型: 时钟发生器
PLL:
输入: 时钟,晶体
输出: CMOS
电路数: 1
比率 - 输入:输出: 2:1
差分 - 输入:输出: 无/无
频率 - 最大: 2.048MHz
除法器/乘法器: 是/无
电源电压: 3.15 V ~ 3.45 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 带卷 (TR)
MK1581-01
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
VCXO AND SYNTHESIZER
IDT LOW PHASE NOISE T1/E1 CLOCK GENERATOR
9
MK1581-01
REV F 051310
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85
° C
Note 1: Minimum high or low time of input clock.
Note 2: The input to output clock skew is not controlled nor predictable and will change between power up cycles.
Because it is dependent on the phase relationship between the output and feedback divider states following power
up, the input to output clock skew will remain stable during a given power up cycle. If controlled input to output skew
is desired for this output clock frequency please refer to the MK2049 or MK2069 products.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
VCXO Crystal Pull Range
fXP
Using Recommended
Crystal
-115
+115
ppm
VCXO Crystal Nominal
Frequency
fX
24.704
24.576
MHz
Input Jitter Tolerance
tji
In reference to input
clock period
0.4
UI
Input pulse width (1)
tpi
10
ns
Output Frequency Error
FOUT
ICLK = 0 ppm error
0
ppm
Output Duty Cycle (% high
time)
tOD
Measured at VDD/2,
CL=15 pF
40
60
%
Output Rise Time
tOR
0.8 to 2.0V, CL=15 pF
1.5
ns
Output Fall Time
tOF
2.0 to 0.8V, CL=15 pF
1.5
ns
Skew, Input to Output Clock
tIO
Note 2
Cycle Jitter (short term jitter)
tja
Peak to Peak
150
ps p-p
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
θJA
Still air
78
° C/W
θJA
1 m/s air flow
70
° C/W
θJA
3 m/s air flow
68
° C/W
Thermal Resistance Junction to Case
θJC
37
° C/W
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