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参数资料
| 型号： | MK2049-11SITR |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | 0.300 INCH, SOIC-20 |
| 文件页数： | 12/13页 |
| 文件大小： | 166K |
| 代理商： | MK2049-11SITR |
Communications Clock PLL
MDS 2049-11 C
8
Revision 021402
Integrated Circuit Systems, Inc. q 525 Race Street San Jose, CA 95126 q tel (408) 295-9800 q
www.icst.com
MK2049-11
than 32 ppm, the MK2049-11 may operate properly
without these adjustment capacitors. However, ICS
recommends that these capacitors be included to
minimize the effects of variation in individual crystals,
included those induced by temperature and aging. The
value of these capacitors (typically 0-4 pF) is
determined once for a given board layout, using the
procedure described in the section titled “Optimization
of Crystal Load Capacitors”.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No via’s should be used
between the decoupling capacitor and VDD pin. The
PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite chip and bulk decoupling from
the device is less critical.
2) The loop filter components must also be placed
close to the CAP1 and CAP2 pins. C2 should be
closest to the device. Coupling of noise from other
system signal traces should be minimized by keeping
traces short and away from active signal traces. Use of
vias should be avoided.
3) The external crystal should be mounted as close the
device as possible, on the component side of the
board. This will keep the crystal PCB traces short
which will minimize parasitic load capacitance on the
crystal, and noise pickup. The crystal traces should be
spaced away from each other and should use minimum
trace width. There should be no signal traces near the
crystal or the traces. Also refer to the Optional Crystal
Shielding section that follows.
4) To minimize EMI the 33
series termination resistor,
if needed, should be placed close to the clock output.
5) All components should be on the same side of the
board, minimizing vias through other signal layers (the
ferrite bead and bulk decoupling capacitor may be
mounted on the back). Other signal traces should be
routed away from the MK2049-11. This includes signal
traces on PCB just underneath the device, or on layers
adjacent to the ground plane layer used by the device.
6) Because each input selection pin includes an
internal pull-up device, those inputs requiring a logic
high state (“1”) can be left unconnected. The pins
requiring a logic low state (“0”) can be connected
directly to ground.
Optional Crystal Shielding
The crystal and connection traces to pins X1 and X2
are sensitive to noise pickup. In applications that
especially sensitive to noise, such as SONET or G-Bit
ethernet transceivers, some or all of the following
crystal shielding techniques may be considered. This is
especially important when the MK2049-11 is placed
near high speed logic or signal traces, and when the
VCXO loop bandwidth is below 10 Hz.
1) The metal layer underneath the crystal section
should be the ground layer. Remove all other layers
that are above. This ground layer will help shield the
crystal circuit from other system noise sources. As an
alternative, all layers underneath the crystal can be
removed, however this is not recommended if there are
adjacent PCBs that can induce noise into the
unshielded crystal circuit.
2) Add a through-hole for the optional third lead offered
by the crystal manufacturer (case ground). The
requirement for this third lead can be made at
prototype evaluation. The crystal is less sensitive to
system noise interference when the case is grounded.
3) Add a ground trace around the crystal circuit to
shield from other active traces on the component layer.
The external crystal is particularly sensitive to other
system clock sources that are at or near the crystal
frequency since it will try to lock to the interfering clock
source. This can adversely affect crystal operation if
the VCXO loop bandwidth is low, such as under 10 Hz.
It is good practice in general to keep the crystal away
from other clock sources.
The ICS Applications Note MAN05 may also be
referenced for additional suggestions on layout of the
crystal section.
Optimization of Crystal Load
Capacitors
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| MK2049-11SITRLF | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-11SI | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2049-34 | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-34A | 制造商:ICS 制造商全称:ICS 功能描述:3.3 Volt Communications Clock VCXO PLL |
| MK2049-34SAI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2049-34SAILF | 功能描述:时钟合成器/抖动清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| MK2049-34SAILFTR | 功能描述:时钟合成器/抖动清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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