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参数资料
| 型号： | MK2049-35SI |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | 0.300 INCH, SOIC-20 |
| 文件页数： | 7/9页 |
| 文件大小： | 112K |
| 代理商： | MK2049-35SI |
MK2049-35
3.3 V Communications Clock PLL
MDS 2049-35 B
7
Revision 081401
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Determining the Crystal Frequency Adjustment Capacitors
To determine the crystal adjustment capacitor values, you will need a PC board of your final layout, a frequency
counter capable of less than 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals
which you plan to use in production, along with measured initial accuracy for each crystal at the specified load
capacitance, CL .
To determine the value of the crystal capacitors:
1. Connect VDD of the MK2049 to 3.3 V. Connect pin 18 of the MK2049 to the second power supply. Adjust the
voltage on pin 18 to 0.0 V. Measure and record the frequency of the CLK or CLK/2 output .
2. Adjust the voltage on pin 18 to 3.3 V. Measure and record the frequency of the same output.
To calculate the centering error:
Centering error = 106
(f3.3V
ftarget) + (f0.0V - ftarget)
ftarget
- errorxtal
Where ftarget = 44.736000 MHz, for example, and errorxtal =
actual initial accuracy (in ppm) of the
crystal being measured.
If the centering error is less than ±15 ppm, no adjustment is needed. If the centering error is more than 15 ppm
negative, the PC board has too much stray capacitance and will need to be redone with a new layout to reduce stray
capacitance. (The crystal may be re-specified to a lower load capacitance instead. Contact ICS for details.) If the
centering error is more than 15 ppm positive, add identical fixed centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
External Capacitor = 2*(centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value, assume it is
30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is acceptably low (less than
±15 ppm).
The ICS applications department can perform this procedure on your board. Call us at 408–295–9800, and we will
arrange for you to send us a PC board (stuffed or unstuffed) and one of your crystals. We will calculate the value of
capacitors needed.
EXTERNAL COMPONENT SELECTION (continued)
相关PDF资料 |
PDF描述 |
|---|---|
| MK2049-44SI | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45ASITR | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45SITR | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45SILFTR | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2058-01SILF | OTHER CLOCK GENERATOR, PDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2049-35SITR | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36 | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36SI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2049-36SILF | 功能描述:时钟发生器及支持产品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK2049-36SILFTR | 功能描述:时钟合成器/抖动清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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