参数资料
型号: MK2049-35SITR
元件分类: 时钟产生/分配
英文描述: 49.152 MHz, OTHER CLOCK GENERATOR, PDSO20
封装: 0.300 INCH, SOIC-20
文件页数: 5/9页
文件大小: 112K
代理商: MK2049-35SITR
MK2049-35
3.3 V Communications Clock PLL
MDS 2049-35 B
5
Revision 081401
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
OPERATING MODES
The MK2049-35 has two operating modes: External and Buffer. Although both modes use an input clock to
generate various output clocks, there are important differences in their input and crystal requirements.
External Mode
The MK2049-35 accepts an external 8 kHz clock and will produce a number of common communication clock
frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as narrow as 10
ns is acceptable.
Buffer Mode
Unlike the other mode that accepts only a single specified input frequency, Buffer Mode will accept a wider range of
input clocks. The input jitter is attenuated, and the outputs on CLK and CLK/2 also provide the option of getting x1,
x2, or 1/2 of the input frequency. For example, this mode can be used to remove the jitter from a 27 MHz clock,
generating low-jitter 27 MHz and 54 MHz outputs.
FREQUENCY LOCKING TO THE INPUT
In all modes, the output clocks are frequency-locked to the input. The output will remain at the specified output
frequency as long as the combined variation of the input frequency and the crystal does not exceed 100 ppm. For
example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the input frequency can vary by
up to 60 ppm and still have the output clock remain frequency-locked.
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相关代理商/技术参数
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