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参数资料
| 型号： | MK2049-36SILFTR |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 155.52 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | 0.300 INCH, SOIC-20 |
| 文件页数： | 4/7页 |
| 文件大小： | 137K |
| 代理商： | MK2049-36SILFTR |
3.3 Volt Communications Clock PLL
MDS 2049-36 D
4
Revision 031505
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126 tel (408) 297-1201
www.icst.com
MK2049-36
Frequency Locking to the Input
In all modes, the output clocks are frequency-locked to the input. The outputs will remain at the specified output
frequency as long as the combined variation of the input frequency and the crystal does not exceed 100 ppm. For
example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the input frequency can vary
by up to 60 ppm and still have the output clock remain frequency-locked.
PC Board Layout
A proper board layout is critical to the successful use of the MK2049. In particular, the CAP1 and CAP2 pins are
very sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as possible and
the two capacitors and resistor must be mounted next to the device as shown below. The capacitor shown between
pins 15 and 17, and the one between pins 4 and 7 are the power supply decoupling capacitors. The high frequency
output clocks on pins 8 and 9 should have a series termination of 33
connected close to the pin. Additional
improvements will come from keeping all components on the same side of the board, minimizing vias through other
signal layers, and routing other signals away from the MK2049. You may also refer to application note MAN05 for
additional suggestions on layout of the crystal selection.
The crystal traces should include pads for small capacitors from X1 and X2 to ground. These are used to adjust the
stray capacitance of the board to match the crystal load capacitance. The typical telecom reference frequency is
accurate to much less than 1 ppm, so the MK2049 may lock and run properly even if the board capacitance is not
adjusted with these fixed capacitors. However, ICS recommends that the adjustment capacitors be included to
minimize the effects of variation in individual crystals, temperature, and aging. The value of these capacitors
(typically 0 - 4 pF) is determined once for a given board layout, using the procedure found in application note
External Component Selection
The MK2049-36 requires a minimum number of external components for proper operation. Decoupling capacitors
of 0.01
F must be connected between VDD and GND pins close to the chip (especially pins 4 and 7, 15 and 17),
and 33
series terminating resistors should be used on clock outputs with traces longer than one inch (assuming
50
traces). The selection of additional external components is described in the following sections.
16
1
15
2
14
3
13
4
12
5
11
6
7
8
9
10
20
19
18
17
G
ca
p
ca
p
resist
cap
ca
p
ca
p
resist
V
G
cap
ca
p
Optional -
see text
Cutout in ground and power plane.
Route all traces away from this area.
V
= connect to VDD
G
= connect to GND
Figure 2. Typical MK2049-34 Layout
相关PDF资料 |
PDF描述 |
|---|---|
| MK2049-36SI | 155.52 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2059-01SILFTR | 25.92 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2059-01SILF | 25.92 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2702STR | 27 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK2702SLF | 27 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2049-36SITR | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2049-45 | 制造商:ICS 制造商全称:ICS 功能描述:3.3V Communications Clock PLL |
| MK2049-45ASI | 功能描述:IC CLK PLL COMM 3.3V 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2049-45ASILF | 功能描述:时钟发生器及支持产品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK2049-45ASILFTR | 功能描述:时钟发生器及支持产品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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