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参数资料
| 型号： | MK2049-36SILFTR |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 155.52 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | 0.300 INCH, SOIC-20 |
| 文件页数： | 5/7页 |
| 文件大小： | 137K |
| 代理商： | MK2049-36SILFTR |
3.3 Volt Communications Clock PLL
MDS 2049-36 D
5
Revision 031505
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126 tel (408) 297-1201
www.icst.com
MK2049-36
Loop Filter
Information on how to configure the external loop filter (connected between pins CAP1 and CAP2) can be found on
our web site at http://www.icst.com under “Design Resources”, then select “Calculators”.
Crystal Operation
The MK2049-36 operates by phase locking the input signal to a VCXO which consists of the recommended pullable
VCXO crystals and the integrated VCXO oscillator circuit on the MK2049. To achieve the best performance and
reliability, the layout guidelines shown on the previous page should be closely followed.
The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected to it.
The MK2049 has variable load capacitors on-chip which “pull” or change the frequency of the crystal. External stray
capacitance must be kept to a minimum to ensure maximum pullability of the crystal. To achieve this, the layout
should use short traces between the MK2049 and the crystal.
For the VCXO to operate correctly, a pullable crystal must be used. For more information, including a list of
approved crystals, please refer to application note MAN05 (http://www.icst.com/appnotes/man05.htm).
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2049-36. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
-40 to +85
°C
Storage Temperature
-65 to +150
°C
Junction Temperature
175
°C
Soldering Temperature
250
°C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
-40
+85
°C
Power Supply Voltage (measured in respect to GND)
+3.15
+3.3
+3.45
V
相关PDF资料 |
PDF描述 |
|---|---|
| MK2049-36SI | 155.52 MHz, OTHER CLOCK GENERATOR, PDSO20 |
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| MK2059-01SILF | 25.92 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2702STR | 27 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK2702SLF | 27 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2049-36SITR | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2049-45 | 制造商:ICS 制造商全称:ICS 功能描述:3.3V Communications Clock PLL |
| MK2049-45ASI | 功能描述:IC CLK PLL COMM 3.3V 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2049-45ASILF | 功能描述:时钟发生器及支持产品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK2049-45ASILFTR | 功能描述:时钟发生器及支持产品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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