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参数资料
| 型号： | MK2058-01SILFTR |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | 0.300 INCH, SOIC-20 |
| 文件页数： | 6/10页 |
| 文件大小： | 164K |
| 代理商： | MK2058-01SILFTR |
Communications Clock Jitter Attenuator
MDS 2058-01 C
5
Revision 050803
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ●
www.icst.com
MK2058-01
A “normalized” PLL loop bandwidth may be calculated
as follows:
The “normalized” bandwidth equation above does not
take into account the effects of damping factor or the
second pole. However, it does provide a useful
approximation of filter performance.
The loop damping factor is calculated as follows:
Where:
RS = Value of resistor in loop filter (Ohms)
ICP = Charge pump current (amps)
(refer to Charge Pump Current Table, below)
N = Crystal multiplier shown in the above table
CS = Value of capacitor C1 in loop filter (Farads)
As a general rule, the following relationship should be
maintained between components C1 and C2 in the loop
filter:
Charge Pump Current Table
Special considerations must be made in choosing loop
www.icst.com.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
W trace (a
commonly used trace impedance), place a 33
W resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
W. (The optional series termination resistor
is not shown in the External Component Schematic.)
Decoupling Capacitors
As with any high performance mixed-signal IC, the
MK2058-01 must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the MK2058-01 should use one common connection to
the PCB power plane as shown in the diagram on the
next page. The ferrite bead and bulk capacitor help
reduce lower frequency noise in the supply that can
lead to output clock phase modulation.
Recommended Power Supply Connection
for Optimal Device Performance
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground, shown as CL in the External Component
Schematic. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
RSET
Charge Pump Current
(ICP)
1.4 M
W
10
mA
680 k
W
20
mA
540 k
W
25
mA
120 k
W
100
mA
NBW
RS ICP
575
N
---------------------------------------
=
Damping Factor
RS
625
I
CP
CS
N
-----------------------------------------
=
CP
CS
20
------
=
C onnection to 3.3V
Pow er Plane
Ferrite
Bead
B ulk D ecoupling C apac itor
(such as 1
F Tantalum)
V DD P in
0.01
F Decoupling Capacitors
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK205801SITR | 制造商:Integrated Device Technology Inc 功能描述: |
| MK2058-01SITR | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2059-01 | 制造商:ICS 制造商全称:ICS 功能描述:VCXO-Based Frame Clock Frequency Translator |
| MK2059-01SI | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2059-01SILF | 功能描述:时钟合成器/抖动清除器 VCXO-BASED FRAME CLK FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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