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参数资料
| 型号： | MK2058-01SILFTR |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | 0.300 INCH, SOIC-20 |
| 文件页数： | 7/10页 |
| 文件大小： | 164K |
| 代理商： | MK2058-01SILFTR |
Communications Clock Jitter Attenuator
MDS 2058-01 C
6
Revision 050803
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ●
www.icst.com
MK2058-01
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no via’s)
been the crystal and device.
In most cases the load capacitors will not be required.
They should not be stuffed on the prototype evaluation
board as the indiscriminate use of these trim capacitors
will typically cause more crystal centering error than
their absence. If the need for the load capacitors is later
determined, the values will fall within the 1-4 pf range.
The need for, and value of, these trim capacitors can
only be determined at prototype evaluation. Please
refer to MAN05 for the procedure to determine the
component values.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed. Please also refer to the Recommended PCB
Layout drawing on Page 7.
1) Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via. Distance of
the ferrite bead and bulk decoupling from the device is
less critical.
2) The loop filter components must also be placed
close to the CHGP and VIN pins. CP should be closest
to the device. Coupling of noise from other system
signal traces should be minimized by keeping traces
short and away from active signal traces. Use of vias
should be avoided.
3) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
4) To minimize EMI the 33
W series termination resistor,
if needed, should be placed close to the clock output.
5) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the MK2058-01.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
The ICS Applications Note MAN05 may also be
referenced for additional suggestions on layout of the
crystal section.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK205801SITR | 制造商:Integrated Device Technology Inc 功能描述: |
| MK2058-01SITR | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2059-01 | 制造商:ICS 制造商全称:ICS 功能描述:VCXO-Based Frame Clock Frequency Translator |
| MK2059-01SI | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2059-01SILF | 功能描述:时钟合成器/抖动清除器 VCXO-BASED FRAME CLK FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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